diff for duplicates of <b3a6afa2e818d31dc60632615215a88449fb78bf.camel@mediatek.com> diff --git a/N1/2.bin b/N1/2.bin new file mode 100644 index 0000000..09a925a --- /dev/null +++ b/N1/2.bin @@ -0,0 +1,49 @@ +<html><body><p> +<pre> +On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote: +> Due to the path mux design of the MT8196, the following components +> need to be added to support Picture Quality (PQ) in the main display +> path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0. + +Reviewed-by: CK Hu <ck.hu@mediatek.com> + +>  +> Signed-off-by: Sunny Shen <sunny.shen@mediatek.com> +> --- +>  drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++++++ +>  1 file changed, 7 insertions(+) +>  +> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c +> index b810a197f58b..1c97dc46ae70 100644 +> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c +> @@ -242,6 +242,13 @@ static const unsigned int mt8196_mtk_ddp_ovl0_main[] = { +>   +>  static const unsigned int mt8196_mtk_ddp_disp0_main[] = { +>  DDP_COMPONENT_DLI_ASYNC0, +> +DDP_COMPONENT_MDP_RSZ0, +> +DDP_COMPONENT_TDSHP0, +> +DDP_COMPONENT_CCORR0, +> +DDP_COMPONENT_CCORR1, +> +DDP_COMPONENT_GAMMA0, +> +DDP_COMPONENT_POSTMASK0, +> +DDP_COMPONENT_DITHER0, +>  DDP_COMPONENT_DLO_ASYNC1, +>  }; +>   + + +</pre> +</p></body></html><!--type:text--><!--{--><pre>************* MEDIATEK Confidentiality Notice ******************** +The information contained in this e-mail message (including any +attachments) may be confidential, proprietary, privileged, or otherwise +exempt from disclosure under applicable laws. It is intended to be +conveyed only to the designated recipient(s). Any use, dissemination, +distribution, printing, retaining or copying of this e-mail (including its +attachments) by unintended recipient(s) is strictly prohibited and may +be unlawful. If you are not an intended recipient of this e-mail, or believe +that you have received this e-mail in error, please notify the sender +immediately (by replying to this e-mail), delete any and all copies of +this e-mail (including any attachments) from your system, and do not +disclose the content of this e-mail to any other person. Thank you! +</pre><!--}--> diff --git a/N1/2.hdr b/N1/2.hdr new file mode 100644 index 0000000..da1f671 --- /dev/null +++ b/N1/2.hdr @@ -0,0 +1,3 @@ +Content-Type: text/html; + charset="utf-8" +Content-Transfer-Encoding: base64 diff --git a/a/content_digest b/N1/content_digest index 5d469e2..94488a2 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -21,7 +21,7 @@ linux-mediatek@lists.infradead.org <linux-mediatek@lists.infradead.org> matthias.bgg@gmail.com <matthias.bgg@gmail.com> " p.zabel@pengutronix.de <p.zabel@pengutronix.de>\0" - "\00:1\0" + "\01:1\0" "b\0" "On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:\n" "> Due to the path mux design of the MT8196, the following components\n" @@ -54,5 +54,56 @@ "> \tDDP_COMPONENT_DLO_ASYNC1,\n" "> };\n" > + "\01:2\0" + "b\0" + "<html><body><p>\r\n" + "<pre>\r\n" + "On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:\r\n" + "> Due to the path mux design of the MT8196, the following components\r\n" + "> need to be added to support Picture Quality (PQ) in the main display\r\n" + "> path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.\r\n" + "\r\n" + "Reviewed-by: CK Hu <ck.hu@mediatek.com>\r\n" + "\r\n" + "> \r\n" + "> Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>\r\n" + "> ---\r\n" + ">  drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++++++\r\n" + ">  1 file changed, 7 insertions(+)\r\n" + "> \r\n" + "> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c\r\n" + "> index b810a197f58b..1c97dc46ae70 100644\r\n" + "> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c\r\n" + "> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c\r\n" + "> @@ -242,6 +242,13 @@ static const unsigned int mt8196_mtk_ddp_ovl0_main[] = {\r\n" + ">  \r\n" + ">  static const unsigned int mt8196_mtk_ddp_disp0_main[] = {\r\n" + ">  DDP_COMPONENT_DLI_ASYNC0,\r\n" + "> +DDP_COMPONENT_MDP_RSZ0,\r\n" + "> +DDP_COMPONENT_TDSHP0,\r\n" + "> +DDP_COMPONENT_CCORR0,\r\n" + "> +DDP_COMPONENT_CCORR1,\r\n" + "> +DDP_COMPONENT_GAMMA0,\r\n" + "> +DDP_COMPONENT_POSTMASK0,\r\n" + "> +DDP_COMPONENT_DITHER0,\r\n" + ">  DDP_COMPONENT_DLO_ASYNC1,\r\n" + ">  };\r\n" + ">  \r\n" + "\r\n" + "\r\n" + "</pre>\r\n" + "</p></body></html><!--type:text--><!--{--><pre>************* MEDIATEK Confidentiality Notice ********************\r\n" + "The information contained in this e-mail message (including any \r\n" + "attachments) may be confidential, proprietary, privileged, or otherwise\r\n" + "exempt from disclosure under applicable laws. It is intended to be \r\n" + "conveyed only to the designated recipient(s). Any use, dissemination, \r\n" + "distribution, printing, retaining or copying of this e-mail (including its \r\n" + "attachments) by unintended recipient(s) is strictly prohibited and may \r\n" + "be unlawful. If you are not an intended recipient of this e-mail, or believe \r\n" + "that you have received this e-mail in error, please notify the sender \r\n" + "immediately (by replying to this e-mail), delete any and all copies of \r\n" + "this e-mail (including any attachments) from your system, and do not\r\n" + "disclose the content of this e-mail to any other person. Thank you!\r\n" + </pre><!--}--> -f3963ec95926f559d6027208092cde97898db4be8e4a443b81136f32bb7cc084 +5ab71e515b42aec3c421bb1fcc2fed615db7813eccd4da6b6c26c70201167e27
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