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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b945816f2sm322493405e9.8.2026.08.31.01.37.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 31 Aug 2026 01:37:52 -0700 (PDT) Message-ID: Date: Mon, 31 Aug 2026 10:37:51 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC v5 26/28] hw/arm/smmuv3: Initialize the secure register bank To: Tao Tang , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Mostafa Saleh , Chao Liu , Jim MacArthur References: <20260813161515.2788900-1-tangtao1634@phytium.com.cn> <20260813162624.2809349-5-tangtao1634@phytium.com.cn> From: Eric Auger In-Reply-To: <20260813162624.2809349-5-tangtao1634@phytium.com.cn> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: SPjBL3SR075go2B0yvtCe71TTfNyD3S2xQEqPEKc72E_1788165474 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 8/13/26 6:26 PM, Tao Tang wrote: > Initialize the secure register bank (SMMU_SEC_SID_S) with sane default > values during the SMMU's reset sequence. > > This change ensures that key fields, such as the secure ID registers, > GBPA reset value, and queue entry sizes, are set to a known-good state. > The SECURE_IMPL attribute of the S_IDR1 register will be introduced > later via device properties. what about SEL2 then? Do you eventually target this in this series? > > This is a necessary step to prevent undefined behavior when secure SMMU > features are subsequently enabled and used by software. > > Signed-off-by: Tao Tang > Reviewed-by: Pierrick Bouvier > --- > hw/arm/smmuv3.c | 29 ++++++++++++++++++++++++++++- > 1 file changed, 28 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 2375b7a17a0..7e7376c65e2 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -293,6 +293,7 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info) > static void smmuv3_init_id_regs(SMMUv3State *s) > { > SMMUv3RegBank *bank = smmuv3_bank(s, SMMU_SEC_SID_NS); > + SMMUv3RegBank *sbank = smmuv3_bank(s, SMMU_SEC_SID_S); > > /* Based on sys property, the stages supported in smmu will be advertised.*/ > if (s->stage && !strcmp("2", s->stage)) { > @@ -339,7 +340,14 @@ static void smmuv3_init_id_regs(SMMUv3State *s) > bank->idr[5] = FIELD_DP32(bank->idr[5], IDR5, GRAN4K, 1); > bank->idr[5] = FIELD_DP32(bank->idr[5], IDR5, GRAN16K, 1); > bank->idr[5] = FIELD_DP32(bank->idr[5], IDR5, GRAN64K, 1); > - s->aidr = 0x1; > + > + /* Initialize Secure bank */ > + memset(sbank->idr, 0, sizeof(sbank->idr)); > + /* No stall */ > + sbank->idr[0] = FIELD_DP32(sbank->idr[0], S_IDR0, STALL_MODEL, 1); > + > + sbank->idr[1] = FIELD_DP32(sbank->idr[1], S_IDR1, S_SIDSIZE, what about S_IDR3.SAMS? > + SMMU_IDR1_SIDSIZE); > smmuv3_accel_idr_override(s); > } > > @@ -352,6 +360,7 @@ bool smmuv3_ats_enabled(SMMUv3State *s) > static void smmuv3_reset(SMMUv3State *s) > { > SMMUv3RegBank *bank = smmuv3_bank(s, SMMU_SEC_SID_NS); > + SMMUv3RegBank *sbank = smmuv3_bank(s, SMMU_SEC_SID_S); > > bank->cmdq.base = deposit64(bank->cmdq.base, 0, 5, SMMU_CMDQS); > bank->cmdq.prod = 0; > @@ -371,6 +380,24 @@ static void smmuv3_reset(SMMUv3State *s) > bank->gerrorn = 0; > bank->gbpa = SMMU_GBPA_RESET_VAL; > > + sbank->cmdq.base = deposit64(sbank->cmdq.base, 0, 5, SMMU_CMDQS); > + sbank->cmdq.prod = 0; > + sbank->cmdq.cons = 0; > + sbank->cmdq.entry_size = sizeof(struct Cmd); > + sbank->eventq.base = deposit64(sbank->eventq.base, 0, 5, SMMU_EVENTQS); > + sbank->eventq.prod = 0; > + sbank->eventq.cons = 0; > + sbank->eventq.entry_size = sizeof(struct Evt); > + > + sbank->features = 0; > + sbank->sid_split = 0; > + sbank->cr[0] = 0; > + sbank->cr0ack = 0; > + sbank->irq_ctrl = 0; > + sbank->gerror = 0; > + sbank->gerrorn = 0; > + sbank->gbpa = SMMU_GBPA_RESET_VAL; > + > s->aidr = 0x1; > s->statusr = 0; > } Thanks Eric