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Sat, 05 Apr 2025 02:09:25 -0700 (PDT) Received: from [192.168.68.110] ([177.170.227.223]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-739d97ee6b3sm4981067b3a.53.2025.04.05.02.09.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 05 Apr 2025 02:09:24 -0700 (PDT) Message-ID: Date: Sat, 5 Apr 2025 06:09:20 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 03/12] target/riscv: Add vext_check_input_eew to check mismatched input EEWs encoding constraint To: Max Chou , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , antonb@tenstorrent.com References: <20250329144446.2619306-1-max.chou@sifive.com> <20250329144446.2619306-4-max.chou@sifive.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20250329144446.2619306-4-max.chou@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 3/29/25 11:44 AM, Max Chou wrote: > According to the v spec, a vector register cannot be used to provide source > operands with more than one EEW for a single instruction. > > Signed-off-by: Max Chou > --- > target/riscv/insn_trans/trans_rvv.c.inc | 29 +++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index e630f8661e1..70c19c49ae4 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -379,6 +379,35 @@ static bool vext_check_ld_index(DisasContext *s, int vd, int vs2, > return ret; > } > > +/* > + * Check whether a vector register is used to provide source operands with > + * more than one EEW for the vector instruction. > + * Returns true if the instruction has valid encoding > + * Returns false if encoding violates the mismatched input EEWs constraint > + */ > +static bool vext_check_input_eew(DisasContext *s, int vs1, uint8_t eew_vs1, > + int vs2, uint8_t eew_vs2, int vm) > +{ > + bool is_valid = true; > + int8_t emul_vs1 = eew_vs1 - s->sew + s->lmul; > + int8_t emul_vs2 = eew_vs2 - s->sew + s->lmul; > + > + /* When vm is 0, vs1 & vs2(EEW!=1) group can't overlap v0 (EEW=1) */ > + if ((vs1 != -1 && !require_vm(vm, vs1)) || > + (vs2 != -1 && !require_vm(vm, vs2))) { > + is_valid = false; > + } > + > + /* When eew_vs1 != eew_vs2, check whether vs1 and vs2 are overlapped */ > + if ((vs1 != -1 && vs2 != -1) && (eew_vs1 != eew_vs2) && > + is_overlapped(vs1, 1 << MAX(emul_vs1, 0), > + vs2, 1 << MAX(emul_vs2, 0))) { > + is_valid = false; > + } > + > + return is_valid; > +} > + Code LGTM but the patch won't compile on its own because there's no callers for it: In file included from ../target/riscv/translate.c:1182: ../target/riscv/insn_trans/trans_rvv.c.inc:388:13: error: ‘vext_check_input_eew’ defined but not used [-Werror=unused-function] 388 | static bool vext_check_input_eew(DisasContext *s, int vs1, uint8_t eew_vs1, | ^~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors ninja: build stopped: subcommand failed. We want each patch to be "buildable" and with test passing to make our lives easier when doing bisects. You can merge this patch with patch 4 to introduce the new function and add its first callers. Thanks, Daniel > static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm) > { > return require_vm(vm, vd) &&