From: Javier Carrasco <javier.carrasco.cruz@gmail.com>
To: Ciprian Hegbeli <ciprian.hegbeli@analog.com>,
Lars-Peter Clausen <lars@metafoo.de>,
Michael Hennerich <Michael.Hennerich@analog.com>,
Jonathan Cameron <jic23@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Kim Seer Paller <kimseer.paller@analog.com>,
Antoniu Miclaus <antoniu.miclaus@analog.com>,
linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] iio: frequency: Add ADF4382
Date: Thu, 14 Nov 2024 14:27:46 +0100 [thread overview]
Message-ID: <b56089e4-ee82-4685-9da8-69cfb6471ec0@gmail.com> (raw)
In-Reply-To: <20241114130340.7354-3-ciprian.hegbeli@analog.com>
On 14/11/2024 14:03, Ciprian Hegbeli wrote:
> The ADF4382A is a high performance, ultralow jitter, Frac-N PLL
> with integrated VCO ideally suited for LO generation for 5G applications
> or data converter clock applications. The high performance
> PLL has a figure of merit of -239 dBc/Hz, low 1/f Noise and
> high PFD frequency of 625MHz in integer mode that can achieve
> ultralow in-band noise and integrated jitter. The ADF4382A can
> generate frequencies in a fundamental octave range of 11.5 GHz to
> 21 GHz, thereby eliminating the need for sub-harmonic filters. The
> divide by 2 and 4 output dividers on the part allow frequencies to
> be generated from 5.75GHz to 10.5GHz and 2.875GHz to 5.25GHz
> respectively.
>
> Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
> ---
> drivers/iio/frequency/Kconfig | 11 +
> drivers/iio/frequency/Makefile | 1 +
> drivers/iio/frequency/adf4382.c | 1825 +++++++++++++++++++++++++++++++
> 3 files changed, 1837 insertions(+)
> create mode 100644 drivers/iio/frequency/adf4382.c
...
> +static int _adf4382_set_freq(struct adf4382_state *st)
> +{
> + u32 frac2_word = 0;
> + u32 mod2_word = 0;
> + u64 pfd_freq_hz;
> + u32 frac1_word;
> + u8 clkout_div;
> + u32 read_val;
> + u8 dclk_div1;
> + u8 int_mode;
> + u8 en_bleed;
> + u8 ldwin_pw;
> + u16 n_int;
> + u8 div1;
> + u64 tmp;
> + u64 vco;
> + int ret;
> + u8 var;
> +
> + ret = adf4382_pfd_compute(st, &pfd_freq_hz);
> + if (ret) {
> + dev_err(&st->spi->dev, "PFD frequency is out of range.\n");
> + return ret;
> + }
> +
> + for (clkout_div = 0; clkout_div <= st->clkout_div_reg_val_max; clkout_div++) {
> + tmp = (1 << clkout_div) * st->freq;
> + if (tmp < st->vco_min || tmp > st->vco_max)
> + continue;
> +
> + vco = tmp;
> + break;
> + }
> +
(At least) LLVM/Clang complains about vco for a good reason: you may use
it without proper initialization if the for loop does not assign any
value. I guess you meant it to be initialized to zero in the declaration.
> + if (vco == 0) {
> + dev_err(&st->spi->dev, "Output frequency is out of range.\n");
> + ret = -EINVAL;
> + return ret;
> + }
> +
Best regards,
Javier Carrasco
next prev parent reply other threads:[~2024-11-14 13:27 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-14 13:03 [PATCH 0/2] Add support for ADF4382 Ciprian Hegbeli
2024-11-14 13:03 ` [PATCH 1/2] dt-bindings: iio: frequency: Add ADF4382 Ciprian Hegbeli
2024-11-14 13:49 ` Javier Carrasco
2024-11-14 13:59 ` Javier Carrasco
2024-11-14 14:35 ` Rob Herring (Arm)
2024-11-14 19:55 ` Conor Dooley
2024-11-25 20:04 ` Jonathan Cameron
2024-11-14 13:03 ` [PATCH 2/2] " Ciprian Hegbeli
2024-11-14 13:27 ` Javier Carrasco [this message]
2024-11-25 21:28 ` Jonathan Cameron
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