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X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KtBVnsvrdE3M1GjG31OXAwqdN/gWOE7gpwmKyxALcGNGdfCoYpUfZdQQ5sWF2XQ7t4gFVioAOrlwPez9Er++Mw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS6PR11MB997164 X-OriginatorOrg: intel.com X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Intel-xe" X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On 2026-10-21 10:57, Piórkowski, Piotr wrote: > From: Piotr Piórkowski > > Since ggtt->start was introduced, the GGTT range no longer begins at > address 0, but the PTE accessors still check only the upper bound of > the address. > > Also assert that the address is not below ggtt->start, so that stale or > miscomputed addresses (e.g. after a VF GGTT shift) are caught as well. > > Suggested-by: Tomasz Lis > Signed-off-by: Piotr Piórkowski Reviewed-by: Tomasz Lis -Tomasz > --- > drivers/gpu/drm/xe/xe_ggtt.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c > index 773777afc68a2..2d890fe74c1b0 100644 > --- a/drivers/gpu/drm/xe/xe_ggtt.c > +++ b/drivers/gpu/drm/xe/xe_ggtt.c > @@ -240,6 +240,7 @@ u64 xe_ggtt_size(struct xe_ggtt *ggtt) > static void xe_ggtt_set_pte(struct xe_ggtt *ggtt, u64 addr, u64 pte) > { > xe_tile_assert(ggtt->tile, !(addr & XE_PTE_MASK)); > + xe_tile_assert(ggtt->tile, addr >= ggtt->start); > xe_tile_assert(ggtt->tile, addr < ggtt->start + ggtt->size); > > writeq(pte, &ggtt->gsm[addr >> XE_PTE_SHIFT]); > @@ -254,6 +255,7 @@ static void xe_ggtt_set_pte_and_flush(struct xe_ggtt *ggtt, u64 addr, u64 pte) > static u64 xe_ggtt_get_pte(struct xe_ggtt *ggtt, u64 addr) > { > xe_tile_assert(ggtt->tile, !(addr & XE_PTE_MASK)); > + xe_tile_assert(ggtt->tile, addr >= ggtt->start); > xe_tile_assert(ggtt->tile, addr < ggtt->start + ggtt->size); > > return readq(&ggtt->gsm[addr >> XE_PTE_SHIFT]);