diff for duplicates of <b602820a-6d5d-5fe1-e100-c1b7be6174bb@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index e3b3e0c..8e7b9f9 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -38,7 +38,7 @@ On 11/12/2017 07:16 PM, Shanker Donthineni wrote: > To avoid the errant behavior, software must execute an ISB immediately > prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0. > -> Signed-off-by: Shanker Donthineni <shankerd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> +> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org> > --- > Documentation/arm64/silicon-errata.txt | 1 + > arch/arm64/Kconfig | 10 ++++++++++ diff --git a/a/content_digest b/N1/content_digest index 7b1c5c5..2a8691a 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,19 +1,9 @@ "ref\01510535802-2799-1-git-send-email-shankerd@codeaurora.org\0" "ref\01510535802-2799-3-git-send-email-shankerd@codeaurora.org\0" - "ref\01510535802-2799-3-git-send-email-shankerd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org\0" - "From\0Shanker Donthineni <shankerd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" - "Subject\0Re: [PATCH v2 2/2] arm64: Add software workaround for Falkor erratum 1041\0" + "From\0shankerd@codeaurora.org (Shanker Donthineni)\0" + "Subject\0[PATCH v2 2/2] arm64: Add software workaround for Falkor erratum 1041\0" "Date\0Sun, 12 Nov 2017 19:54:10 -0600\0" - "To\0Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>" - Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" - "Cc\0linux-efi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" - Ard Biesheuvel <ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> - Matt Fleming <matt-mF/unelCI9GS6iBeEJttW/XRex20P6io@public.gmane.org> - Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - kvmarm-FPEHb7Xf0XXUo1n7N8X6UoWGPAHP3yOg@public.gmane.org - " Christoffer Dall <christoffer.dall-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi, \n" @@ -56,7 +46,7 @@ "> To avoid the errant behavior, software must execute an ISB immediately\n" "> prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.\n" "> \n" - "> Signed-off-by: Shanker Donthineni <shankerd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\n" + "> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>\n" "> ---\n" "> Documentation/arm64/silicon-errata.txt | 1 +\n" "> arch/arm64/Kconfig | 10 ++++++++++\n" @@ -243,4 +233,4 @@ "Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.\n" Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. -494a88f98268001dd01a267739d1438c8bad901ef5b3a7586091672ef7b9fbac +ee028c7f5077636585e1fb0f739aefd03d1b1ec614c843d2ce015c56bd47cf99
diff --git a/a/1.txt b/N2/1.txt index e3b3e0c..8e7b9f9 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -38,7 +38,7 @@ On 11/12/2017 07:16 PM, Shanker Donthineni wrote: > To avoid the errant behavior, software must execute an ISB immediately > prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0. > -> Signed-off-by: Shanker Donthineni <shankerd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> +> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org> > --- > Documentation/arm64/silicon-errata.txt | 1 + > arch/arm64/Kconfig | 10 ++++++++++ diff --git a/a/content_digest b/N2/content_digest index 7b1c5c5..b9d8b4e 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,19 +1,18 @@ "ref\01510535802-2799-1-git-send-email-shankerd@codeaurora.org\0" "ref\01510535802-2799-3-git-send-email-shankerd@codeaurora.org\0" - "ref\01510535802-2799-3-git-send-email-shankerd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org\0" - "From\0Shanker Donthineni <shankerd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" + "From\0Shanker Donthineni <shankerd@codeaurora.org>\0" "Subject\0Re: [PATCH v2 2/2] arm64: Add software workaround for Falkor erratum 1041\0" "Date\0Sun, 12 Nov 2017 19:54:10 -0600\0" - "To\0Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>" - Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" - "Cc\0linux-efi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" - Ard Biesheuvel <ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> - Matt Fleming <matt-mF/unelCI9GS6iBeEJttW/XRex20P6io@public.gmane.org> - Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - kvmarm-FPEHb7Xf0XXUo1n7N8X6UoWGPAHP3yOg@public.gmane.org - " Christoffer Dall <christoffer.dall-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "To\0Will Deacon <will.deacon@arm.com>" + Marc Zyngier <marc.zyngier@arm.com> + " linux-arm-kernel@lists.infradead.org\0" + "Cc\0linux-efi@vger.kernel.org" + Ard Biesheuvel <ard.biesheuvel@linaro.org> + Matt Fleming <matt@codeblueprint.co.uk> + Catalin Marinas <catalin.marinas@arm.com> + linux-kernel@vger.kernel.org + kvmarm@lists.cs.columbia.edu + " Christoffer Dall <christoffer.dall@linaro.org>\0" "\00:1\0" "b\0" "Hi, \n" @@ -56,7 +55,7 @@ "> To avoid the errant behavior, software must execute an ISB immediately\n" "> prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.\n" "> \n" - "> Signed-off-by: Shanker Donthineni <shankerd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\n" + "> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>\n" "> ---\n" "> Documentation/arm64/silicon-errata.txt | 1 +\n" "> arch/arm64/Kconfig | 10 ++++++++++\n" @@ -243,4 +242,4 @@ "Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.\n" Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. -494a88f98268001dd01a267739d1438c8bad901ef5b3a7586091672ef7b9fbac +4ca635e54d8d86f1de85a9f4cb05857466ad3cb51a5c712c2b7a121d4e3d8b5b
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