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clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On 16/10/2026 12:40 pm, Chen Huei Lok wrote: > Move the mbox_qspi_open() call ahead of DRAM initialization so the QSPI > controller is handed over to the HPS and its reference clock is > configured before the DDR retention path reads the calibration backup > from QSPI during DDR init. > > Signed-off-by: Chen Huei Lok > --- > arch/arm/mach-socfpga/spl_n5x.c | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c > index 381aca6d32f..bb2d6187ffc 100644 > --- a/arch/arm/mach-socfpga/spl_n5x.c > +++ b/arch/arm/mach-socfpga/spl_n5x.c > @@ -105,6 +105,9 @@ void board_init_f(ulong dummy) > hang(); > } > > + if (IS_ENABLED(CONFIG_CADENCE_QSPI)) > + mbox_qspi_open(); > + > #if CONFIG_IS_ENABLED(ALTERA_SDRAM) > ret = uclass_get_device(UCLASS_RAM, 0, &dev); > if (ret) { > @@ -112,8 +115,4 @@ void board_init_f(ulong dummy) > hang(); > } > #endif > - > -#ifdef CONFIG_CADENCE_QSPI > - mbox_qspi_open(); > -#endif > } Reviewed-by: Tien Fong Chee Best regards, Tien Fong