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([2401:4900:1c43:14e:b774:f226:fbad:d915]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7326d58d4d0sm6153580b3a.94.2025.02.18.11.38.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Feb 2025 11:38:21 -0800 (PST) Message-ID: Date: Wed, 19 Feb 2025 01:08:18 +0530 Precedence: bulk X-Mailing-List: linux-openrisc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Queries regarding OpenRISC CPU cache From: Sahil Siddiq To: Stafford Horne Cc: Linux OpenRISC References: <2613c1c6-2a2f-4ceb-8adb-f819961ec61f@gmail.com> <1052b18b-7524-49b4-8ac2-22031bf90d4b@gmail.com> Content-Language: en-US Autocrypt: addr=icegambit91@gmail.com; keydata= xsDNBGcgaYEBDADpKUSKbchLCMdCuZGkuF50/7BiraKc8Ch+mk4T+2+E2/6qXAkalvCkFoqx 3/sa35rconZAFzB/r19e7i3UajIQjATvENrGxqe/IFqcJxo2Jr1HQBwCrsmlQoUCilSC6nDi ejcEIAFytJORDkCcZwLXPjdf5/4pbqVAW5823LB5j5F0TqHAnGY1RhS2V1eBPdRqjAA3xecT zTmLHlkqAXgM2DOot1KbycedZSieCwEykTXMaLC0/3Gyo2Cp1WTWOIyD0hsXpLyFioV4FaX2 Lm+z45Zc4PoNXeC6+l4PdDxixs+saAbadknP+9omwlb+PkMd3esq2wkowTwTJVJK8FCCNTo5 2OArA/ddxcyXY25JHN7vzGooFNW6Bb9YV+lbX6y95ytE3KcAmid73tQrcjlebIpgNAvOMyyZ BgQJY0HSu3DGNZuKtbNM3iTl82TFj7MVgkEffgF83N6XyBqDztIz2lN47/q5wyRi3jda9NDt geI+Nv145HjulO7bI3NT048AEQEAAc0kU2FoaWwgU2lkZGlxIDxpY2VnYW1iaXQ5MUBnbWFp bC5jb20+wsENBBMBCAA3FiEERtYfQYWFu+uAZjYrrzGlXdb6f1cFAmcgaYEFCQWjmoACGwME CwkIBwUVCAkKCwUWAgMBAAAKCRCvMaVd1vp/V/nnC/9KnNIr4a3JW3E/snxv1+XIyUmHBDLn PKBmLDYxO9RJe1xKo/sNmLEno4c8G1F/y12TLV086cpBYGKkE8mPMBABqxuiPG8srwoKc2HW bvoC2Zfeu/WeQ0YqeI9ZEwRhsDGQZ7vc8PnKnEUaPZn6iWW4GeX7dXWeGNrK0wU2B04l2d+M FIKaoPHk8w5Ff++QNcn0YRkm//nYlukHUrMxhNcuc18jaLLftOh7BH/4EbKtTN75KAFePQBi I2CbuC41fchTt12QrPB3yz1GKfudsEMLFHBNeComJNnuolPOq0YSyuKdRO8Jubn5ZqWQeTwj XbG7wTonDc8xe46irOhz36VcjsjSY+PYhVZSeDWeDUZgpaJkBjQDDodIN2eoMwVEyUByos9H mKrqrpBMmylOspAZzqjb5FtOqM0BCxQINdKKiMwRelSb6pHYCrbS0XzpwDUEpp7RWCbHgg+6 Ot72kQCEFxj2LzX9VxF24GGQy9inlUfN51IV04klSibtBuuz/NbOwM0EZyBpgQEMAJelVX4k CtCxD4Ji3FQ8LZs22z7VoUvqIb7Gj2lNvhPeijlqqBkSMIgnSCLxlH4ahqKnEV58IrfVriV0 92zb94Az2nl0r+bZYfvev1qCcVIYxk+pYYcRl5qPXX8XGalrkcBBWmkgTSwzNK9rV4850iVI hsJNel49qen9JwiFYMSKa2MYgdYSbeuuwXwUp0ZHeVFc5RnPK2wxws1xcnsdb9hRXs2UeTEE 0klG3HuXqJ96DzKrCieKHLjs330h+16gDWAFZSEoT7Mh3HFGI2dscVuBstQNgnwUMnsJv8jx c005CfLCjCBnJEhMd2/QFuLwCZv4IdoghKwYw18e61UbX2bFovo9dduD527pD4sFqi7U7ofv aO3yf+ulL6jiKypGvnbiBP3KY3aKxx6pHHH3aDc9eOqCUgrtS3+xt1du4+qxrYqEnrywFoJy 5zqSzbnTTjFpdTbY5SS52fIOktLlAKzEg6V9hkg2r08hC3/L4NVj6I4tsGZlqb2neRlHFmCr bQARAQABwsD8BBgBCAAmFiEERtYfQYWFu+uAZjYrrzGlXdb6f1cFAmcgaYIFCQWjmoACGwwA CgkQrzGlXdb6f1fDIgwAmpB7eL3XNSx3F+gbmksOPMqCU5rEswRedjEt6tBzFTXhdNFfhZTb vCddUNePZnzddgxAnDBcTqI1jx6Go6Hkti/mxJqXSczMYBsImD/lEm47axsADvpnNaEM+tmu m/cMKfpILUpy2Ey7CKXUA1vpzYeUD29EQWi0fxM0arplrVt/uzUdFRFQRn2hCqeDLBLONX1F Adq+re6M0dhKl4a2+erzZRIXh3vIGiDmpJEGrajrhqEnMXFp6toSiMGian94m8H3NT6rB64E JmdHgyjXADFbn2G5Mb6Pwa8KnnK1kYcZ+Pwu9LfMXfgI01Sh/k01hjUVmnpYep4nHUfwXA8r kn6WekD80DYbAfKyFAXQCO/nclZ82RNmJbDRi3AeMFrxKi6KgdGCp1Izhj9USaMOVqcuV2p0 Rsoq+sFqWOKaHWnQHCM9RkynQVqrgUaSawEbGlCP1KIhVmjfjVsmsCaKkUb9T6VeO+ZNe+Pn rPgMe6IIvn24UuW2f6fIt0AaqOWq In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi, On 2/12/25 8:59 PM, Sahil Siddiq wrote: > Hi, > > I have started working on implementing cacheinfo support for OpenRISC, and > I have got a few queries. > > Q1. > Does OpenRISC support multilevel cache hierarchy? I couldn't find anything > in the architecture manual [1] mentioning the possibility of a multilevel > cache hierarchy. I wasn't able to find anything in the verilog implementation > either [2]. > > Q2. > In /sys/devices/system/cpu/cpuX/cache, each indexY directory corresponds > to a CPU cache. According to the OpenRISC 1000 Architecture specification [1], > it is possible to have a unified cache. In such a case, registers controlling > the instruction and data cache represent the same thing (section 9.1 of the > manual). > > Consequently, should there be only one index (i.e. index0), or should there > be 2 index directories (index0 and index1) with identical content? If aunified > cache is used, will the DCP and ICP bits both be set in the UPR register? > > Q3. > Cache-related arithmetic performed in arch/openrisc/kernel/setup.c:setup_cpuinfo() [3] > cannot be avoided. But we can expose this info in sysfs instead of cpuinfo as > specified in this mail [4]. So, I was thinking of moving these calculations to > arch/openrisc/kernel/cacheinfo.c in init_cache_level(). > > What are your thoughts on this? > > Another thing I noticed in the current implementation is that these calculations > are performed for icache and dcache before using the UPR register to check if > they even exist. Should these calculations instead be performed after determining > that they exist? > [...] Building on my previous mail, I noticed another thing: On 1/25/25 1:00 PM, Stafford Horne wrote: > On my x86 machine I see: > > $ tree /sys/devices/system/cpu/cpu0/cache/ > /sys/devices/system/cpu/cpu0/cache/ > ├── index0 > │ ├── coherency_line_size > │ ├── id > │ ├── level > │ ├── number_of_sets > │ ├── physical_line_partition > │ ├── shared_cpu_list > > On or1k I only see (no cache info yet): > > $ tree /sys/devices/system/cpu/cpu0/ > /sys/devices/system/cpu/cpu0/ > |-- of_node -> ../../../../firmware/devicetree/base/cpus/cpu@0 > |-- subsystem -> ../../../../bus/cpu > |-- topology > | |-- core_cpus > | |-- core_cpus_list > | |-- core_id > | |-- core_siblings > | |-- core_siblings_list > | |-- package_cpus > | |-- package_cpus_list > | |-- physical_package_id > | |-- thread_siblings > | `-- thread_siblings_list > `-- uevent > > But we do have some cache info available via cpuinfo: > > $ cat /proc/cpuinfo | head -n16 > processor : 0 > cpu : OpenRISC-13 > revision : 8 > frequency : 20000000 > dcache size : 256 bytes > dcache block size : 16 bytes > dcache ways : 1 > icache size : 32 bytes > icache block size : 16 bytes > icache ways : 2 > immu : 128 entries, 1 ways > dmmu : 128 entries, 1 ways > bogomips : 40.00 > features : orbis32 orfpx32 > While I can see icache and dcache info in /proc/cpuinfo, dmesg reports that the caches have been disabled. OF: reserved mem: Reserved memory: No reserved-memory node in the DT CPU: OpenRISC-13 (revision 8) @20 MHz -- dcache disabled -- icache disabled -- dmmu: 128 entries, 1 way(s) -- immu: 128 entries, 1 way(s) -- additional features: -- power management -- PIC -- timer This is because the value of upr is 0x719 and the value of SPR_UPR_DCP is 0x2. ANDing both values gives 0 which, according to the arch manual [1], means there's no dcache. The same thing applies to icache. Thanks, Sahil [1] https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf (Section 16.3)