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Thu, 28 Nov 2024 04:54:40 -0800 (PST) Received: from [192.168.68.110] ([187.101.65.72]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21521967278sm12753475ad.161.2024.11.28.04.54.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Nov 2024 04:54:39 -0800 (PST) Message-ID: Date: Thu, 28 Nov 2024 09:54:36 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 10/11] target/riscv: Add implied rule for counter delegation extensions To: Atish Patra , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: kaiwenxue1@gmail.com, palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, alistair.francis@wdc.com References: <20241117-counter_delegation-v3-0-476d6f36e3c8@rivosinc.com> <20241117-counter_delegation-v3-10-476d6f36e3c8@rivosinc.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20241117-counter_delegation-v3-10-476d6f36e3c8@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 11/17/24 10:15 PM, Atish Patra wrote: > The counter delegation/configuration extensions depend on the following > extensions. > > 1. Smcdeleg - To enable counter delegation from M to S > 2. S[m|s]csrind - To enable indirect access CSRs > > Add an implied rule so that these extensions are enabled by default > if the sscfg extension is enabled. > > Signed-off-by: Atish Patra > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/cpu.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 82edd28e2e1d..410ca2e3a666 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -2642,6 +2642,16 @@ static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = { > }, > }; > > +static RISCVCPUImpliedExtsRule SSCFG_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_ssccfg), > + .implied_multi_exts = { > + CPU_CFG_OFFSET(ext_smcsrind), CPU_CFG_OFFSET(ext_sscsrind), > + CPU_CFG_OFFSET(ext_smcdeleg), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = { > &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, > &RVM_IMPLIED, &RVV_IMPLIED, NULL > @@ -2659,7 +2669,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = { > &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, > &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, > &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, > - &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, > + &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED, > NULL > }; > >