diff for duplicates of <b6be1531-d8e2-44d1-a81a-6db8f9ae4ad4@kernel.org> diff --git a/a/1.txt b/N1/1.txt index a4181d1..3aca544 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -55,7 +55,7 @@ Nope. Such aliases are board specific. > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a35"; > + enable-method = "psci"; > + device_type = "cpu"; @@ -69,7 +69,7 @@ Nope. Such aliases are board specific. > + next-level-cache = <&l2>; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a35"; > + enable-method = "psci"; > + device_type = "cpu"; @@ -83,7 +83,7 @@ Nope. Such aliases are board specific. > + next-level-cache = <&l2>; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a35"; > + enable-method = "psci"; > + device_type = "cpu"; @@ -97,7 +97,7 @@ Nope. Such aliases are board specific. > + next-level-cache = <&l2>; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a35"; > + enable-method = "psci"; > + device_type = "cpu"; @@ -140,7 +140,7 @@ Fix all your patches: > + method = "smc"; > + }; > + -> + gic: interrupt-controller at 12200000 { +> + gic: interrupt-controller@12200000 { Nope, this cannot be outside of SoC. @@ -169,13 +169,13 @@ Read DTS coding style and order this correctly. > + always-on; > + }; > + -> + soc0: soc at 10000000 { +> + soc0: soc@10000000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + -> + soc0_sram: sram at 10000000 { +> + soc0_sram: sram@10000000 { > + compatible = "mmio-sram"; > + reg = <0x0 0x10000000 0x0 0x20000>; /* 128KiB SRAM on soc0 */ > + ranges = <0x0 0x0 0x0 0x10000000 0x0 0x20000>; @@ -183,13 +183,13 @@ Read DTS coding style and order this correctly. > + #size-cells = <2>; > + no-memory-wc; > + -> + exported at 0 { +> + exported@0 { > + reg = <0 0x0 0 0x20000>; > + export; > + }; > + }; > + -> + syscon0: syscon at 12c02000 { +> + syscon0: syscon@12c02000 { > + compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd"; > + reg = <0x0 0x12c02000 0x0 0x1000>; > + ranges = <0x0 0x0 0 0x12c02000 0 0x1000>; @@ -198,12 +198,12 @@ Read DTS coding style and order this correctly. > + #clock-cells = <1>; > + #reset-cells = <1>; > + -> + silicon-id at 0 { +> + silicon-id@0 { > + compatible = "aspeed,ast2700-silicon-id", "aspeed,silicon-id"; > + reg = <0 0x0 0 0x4>; > + }; > + -> + scu_ic0: interrupt-controller at 1D0 { +> + scu_ic0: interrupt-controller@1D0 { DTS coding style... @@ -214,7 +214,7 @@ DTS coding style... > + interrupt-controller; > + }; > + -> + scu_ic1: interrupt-controller at 1E0 { +> + scu_ic1: interrupt-controller@1E0 { > + #interrupt-cells = <1>; > + compatible = "aspeed,ast2700-scu-ic1"; > + reg = <0 0x1e0 0 0xc>; @@ -222,18 +222,18 @@ DTS coding style... > + interrupt-controller; > + }; > + -> + soc0_rst: reset-controller at 200 { +> + soc0_rst: reset-controller@200 { > + reg = <0 0x200 0 0x40>; > + }; > + -> + soc0_clk: clock-controller at 240 { +> + soc0_clk: clock-controller@240 { > + reg = <0 0x240 0 0x1c0>; > + }; > + }; > + > + }; > + -> + soc1: soc at 14000000 { +> + soc1: soc@14000000 { Wait, what, to socs? @@ -242,7 +242,7 @@ Wait, what, to socs? > + #size-cells = <2>; > + ranges; > + -> + syscon1: syscon at 14c02000 { +> + syscon1: syscon@14c02000 { > + compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd"; > + reg = <0x0 0x14c02000 0x0 0x1000>; > + ranges = <0x0 0x0 0x0 0x14c02000 0x0 0x1000>; @@ -251,16 +251,16 @@ Wait, what, to socs? > + #clock-cells = <1>; > + #reset-cells = <1>; > + -> + soc1_rst: reset-controller at 200 { +> + soc1_rst: reset-controller@200 { > + #reset-cells = <1>; > + }; > + -> + soc1_clk: clock-controller at 240 { +> + soc1_clk: clock-controller@240 { > + reg = <0 0x240 0 0x1c0>; > + }; > + }; > + -> + uart12: serial at 14c33b00 { +> + uart12: serial@14c33b00 { > + compatible = "ns16550a"; > + reg = <0x0 0x14c33b00 0x0 0x100>; > + reg-shift = <2>; diff --git a/a/content_digest b/N1/content_digest index 2144f65..42d93d0 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,36 @@ "ref\020240726110355.2181563-1-kevin_chen@aspeedtech.com\0" "ref\020240726110355.2181563-9-kevin_chen@aspeedtech.com\0" "From\0Krzysztof Kozlowski <krzk@kernel.org>\0" - "Subject\0[PATCH v1 08/10] arm64: dts: aspeed: Add initial AST27XX device tree\0" + "Subject\0Re: [PATCH v1 08/10] arm64: dts: aspeed: Add initial AST27XX device tree\0" "Date\0Fri, 26 Jul 2024 13:19:50 +0200\0" - "To\0linux-aspeed@lists.ozlabs.org\0" + "To\0Kevin Chen <kevin_chen@aspeedtech.com>" + robh@kernel.org + krzk+dt@kernel.org + conor+dt@kernel.org + joel@jms.id.au + andrew@codeconstruct.com.au + lee@kernel.org + catalin.marinas@arm.com + will@kernel.org + arnd@arndb.de + olof@lixom.net + soc@kernel.org + mturquette@baylibre.com + sboyd@kernel.org + p.zabel@pengutronix.de + quic_bjorande@quicinc.com + geert+renesas@glider.be + dmitry.baryshkov@linaro.org + shawnguo@kernel.org + neil.armstrong@linaro.org + m.szyprowski@samsung.com + nfraprado@collabora.com + u-kumar1@ti.com + devicetree@vger.kernel.org + linux-arm-kernel@lists.infradead.org + linux-aspeed@lists.ozlabs.org + linux-kernel@vger.kernel.org + " linux-clk@vger.kernel.org\0" "\00:1\0" "b\0" "On 26/07/2024 13:03, Kevin Chen wrote:\n" @@ -63,7 +90,7 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a35\";\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" @@ -77,7 +104,7 @@ "> +\t\t\tnext-level-cache = <&l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a35\";\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" @@ -91,7 +118,7 @@ "> +\t\t\tnext-level-cache = <&l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a35\";\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" @@ -105,7 +132,7 @@ "> +\t\t\tnext-level-cache = <&l2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a35\";\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" @@ -148,7 +175,7 @@ "> +\t\tmethod = \"smc\";\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at 12200000 {\n" + "> +\tgic: interrupt-controller@12200000 {\n" "\n" "Nope, this cannot be outside of SoC.\n" "\n" @@ -177,13 +204,13 @@ "> +\t\talways-on;\n" "> +\t};\n" "> +\n" - "> +\tsoc0: soc at 10000000 {\n" + "> +\tsoc0: soc@10000000 {\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\t#address-cells = <2>;\n" "> +\t\t#size-cells = <2>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tsoc0_sram: sram at 10000000 {\n" + "> +\t\tsoc0_sram: sram@10000000 {\n" "> +\t\t\tcompatible = \"mmio-sram\";\n" "> +\t\t\treg = <0x0 0x10000000 0x0 0x20000>;\t/* 128KiB SRAM on soc0 */\n" "> +\t\t\tranges = <0x0 0x0 0x0 0x10000000 0x0 0x20000>;\n" @@ -191,13 +218,13 @@ "> +\t\t\t#size-cells = <2>;\n" "> +\t\t\tno-memory-wc;\n" "> +\n" - "> +\t\t\texported at 0 {\n" + "> +\t\t\texported@0 {\n" "> +\t\t\t\treg = <0 0x0 0 0x20000>;\n" "> +\t\t\t\texport;\n" "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tsyscon0: syscon at 12c02000 {\n" + "> +\t\tsyscon0: syscon@12c02000 {\n" "> +\t\t\tcompatible = \"aspeed,ast2700-scu0\", \"syscon\", \"simple-mfd\";\n" "> +\t\t\treg = <0x0 0x12c02000 0x0 0x1000>;\n" "> +\t\t\tranges = <0x0 0x0 0 0x12c02000 0 0x1000>;\n" @@ -206,12 +233,12 @@ "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\n" - "> +\t\t\tsilicon-id at 0 {\n" + "> +\t\t\tsilicon-id@0 {\n" "> +\t\t\t\tcompatible = \"aspeed,ast2700-silicon-id\", \"aspeed,silicon-id\";\n" "> +\t\t\t\treg = <0 0x0 0 0x4>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tscu_ic0: interrupt-controller at 1D0 {\n" + "> +\t\t\tscu_ic0: interrupt-controller@1D0 {\n" "\n" "DTS coding style...\n" "\n" @@ -222,7 +249,7 @@ "> +\t\t\t\tinterrupt-controller;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tscu_ic1: interrupt-controller at 1E0 {\n" + "> +\t\t\tscu_ic1: interrupt-controller@1E0 {\n" "> +\t\t\t\t#interrupt-cells = <1>;\n" "> +\t\t\t\tcompatible = \"aspeed,ast2700-scu-ic1\";\n" "> +\t\t\t\treg = <0 0x1e0 0 0xc>;\n" @@ -230,18 +257,18 @@ "> +\t\t\t\tinterrupt-controller;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tsoc0_rst: reset-controller at 200 {\n" + "> +\t\t\tsoc0_rst: reset-controller@200 {\n" "> +\t\t\t\treg = <0 0x200 0 0x40>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tsoc0_clk: clock-controller at 240 {\n" + "> +\t\t\tsoc0_clk: clock-controller@240 {\n" "> +\t\t\t\treg = <0 0x240 0 0x1c0>;\n" "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" "> +\t};\n" "> +\n" - "> +\tsoc1: soc at 14000000 {\n" + "> +\tsoc1: soc@14000000 {\n" "\n" "Wait, what, to socs?\n" "\n" @@ -250,7 +277,7 @@ "> +\t\t#size-cells = <2>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tsyscon1: syscon at 14c02000 {\n" + "> +\t\tsyscon1: syscon@14c02000 {\n" "> +\t\t\tcompatible = \"aspeed,ast2700-scu1\", \"syscon\", \"simple-mfd\";\n" "> +\t\t\treg = <0x0 0x14c02000 0x0 0x1000>;\n" "> +\t\t\tranges = <0x0 0x0 0x0 0x14c02000 0x0 0x1000>;\n" @@ -259,16 +286,16 @@ "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\n" - "> +\t\t\tsoc1_rst: reset-controller at 200 {\n" + "> +\t\t\tsoc1_rst: reset-controller@200 {\n" "> +\t\t\t\t#reset-cells = <1>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tsoc1_clk: clock-controller at 240 {\n" + "> +\t\t\tsoc1_clk: clock-controller@240 {\n" "> +\t\t\t\treg = <0 0x240 0 0x1c0>;\n" "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart12: serial at 14c33b00 {\n" + "> +\t\tuart12: serial@14c33b00 {\n" "> +\t\t\tcompatible = \"ns16550a\";\n" "> +\t\t\treg = <0x0 0x14c33b00 0x0 0x100>;\n" "> +\t\t\treg-shift = <2>;\n" @@ -287,4 +314,4 @@ "Best regards,\n" Krzysztof -9c90b3d9598596aff221bfd03536fadd33fe7ee732d49f2686005215938c74f9 +1c1cf6237cb43a8624d5969145dbcec0032e6c79430a02203f2c42d30ed54547
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