From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: fix per-pipe reads after "cleanup" Date: Thu, 17 Feb 2011 21:08:08 +0000 Message-ID: References: <20110217104053.1a568b5e@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 126E39E740 for ; Thu, 17 Feb 2011 13:08:18 -0800 (PST) In-Reply-To: <20110217104053.1a568b5e@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, 17 Feb 2011 10:40:53 -0800, Jesse Barnes wrote: > In a few places I replaced reads of per-pipe registers with the actual > register offsets themselves (converting I915_READ(reg) to _PIPE(reg)). > Alexey caught this on his 9xx machine because the cursor control write > was affected. A quick audit showed a few more places where I'd borked > a read, so here's a patch to fix things up. Shoot the reviewer. Thanks for finding those needles in the haystack, -Chris -- Chris Wilson, Intel Open Source Technology Centre