From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 1/2] drm/i915: Don't allow ring tail to reach the same cacheline as head Date: Mon, 26 Nov 2012 16:28:33 +0000 Message-ID: References: <1353934099-18685-1-git-send-email-ville.syrjala@linux.intel.com> <1353934099-18685-2-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0580664851==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 7ECD1E5CE4 for ; Mon, 26 Nov 2012 08:28:39 -0800 (PST) In-Reply-To: <1353934099-18685-2-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0580664851== Content-Type: text/plain On Mon, 26 Nov 2012 14:48:18 +0200, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä > > According to BSpec the ring head and tail pointers must not be > on the same cacheline when head > tail. The easiest way to enforce > this is to reduce the reported ring space. I'm going to admit blindness because I don't see that warning in the gen2-gen7 bspecs. Can you please give chapter and verse, and check to see if there is a rationale? -Chris -- Chris Wilson, Intel Open Source Technology Centre --===============0580664851== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0580664851==--