From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: Fix pte updates in ggtt clear range Date: Tue, 27 Nov 2012 08:22:01 +0000 Message-ID: References: <1353995574-1021-1-git-send-email-ben@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 7E50EE5DFF for ; Tue, 27 Nov 2012 00:22:08 -0800 (PST) In-Reply-To: <1353995574-1021-1-git-send-email-ben@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Mon, 26 Nov 2012 21:52:54 -0800, Ben Widawsky wrote: > This bug was introduced by me: > commit e76e9aebcdbfebae8f4cd147e3c0f800d36e97f3 > Author: Ben Widawsky > Date: Sun Nov 4 09:21:27 2012 -0800 > > drm/i915: Stop using AGP layer for GEN6+ > > The existing code uses memset_io which follows memset semantics in only > guaranteeing a write of individual bytes. Since a PTE entry is 4 bytes, > this can only be correct if the scratch page address is 0. Gah. Wasn't there an iowrite32_rep? > This caused unsightly errors when we clear the range at load time, > though I'm not really sure what the heck is referencing that memory > anyway. I caught this is because I believe we have some other bug where > the display is doing reads of memory we feel should be cleared (or we > are relying on scratch pages to be a specific value). That's just because we are no longer disabling outputs before updating the GTT and hence continue to scanout from the BIOS fb during module load. It's a regression that we'll be able to finally fix properly with fastboot - though that will not be without its downsides either. -Chris -- Chris Wilson, Intel Open Source Technology Centre