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[2001:1c00:c1e:bf00:37a3:353b:be90:1238]) by smtp.gmail.com with ESMTPSA id z2sm1419474ejd.44.2021.01.20.13.38.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 Jan 2021 13:38:18 -0800 (PST) Subject: Re: [PATCH v3 3/5] mfd: arizona: Add support for ACPI enumeration of WM5102 connected over SPI To: Andy Shevchenko References: <20210117212252.206115-1-hdegoede@redhat.com> <20210117212252.206115-4-hdegoede@redhat.com> <20210118130227.GI4455@sirena.org.uk> <5ccf48f4-45dc-3a30-3d6a-cce066f01270@redhat.com> <20210118133449.GL4455@sirena.org.uk> From: Hans de Goede Message-ID: Date: Wed, 20 Jan 2021 22:38:17 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=hdegoede@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Cc: Cezary Rojewski , Charles Keepax , Christian Hartmann , ALSA Development Mailing List , patches@opensource.cirrus.com, Jie Yang , Pierre-Louis Bossart , Linux Kernel Mailing List , Liam Girdwood , Mark Brown , Lee Jones X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Hi, On 1/20/21 8:59 PM, Andy Shevchenko wrote: > On Wed, Jan 20, 2021 at 9:18 PM Hans de Goede wrote: >> On 1/18/21 2:34 PM, Mark Brown wrote: >>> On Mon, Jan 18, 2021 at 02:13:50PM +0100, Hans de Goede wrote: >>> >>>> More in general I'm not aware of any (recent-ish) x86 GPIO controllers >>>> not being able to do active low interrupts. In theory we could hit this >>>> code path on ARM devices using ACPI enumeration, but I don't think it >>>> is likely we will see a combination of ARM + ACPI enumeration + >>>> WM5102 + GPIO controller not capable of active-low interrupts. >>> >>> I've not seen this issue on any ARM based systems. >>> >>>> This overriding of the flags definitely is necessary on the Lenovo >>>> devices in question. I could add a >>>> "if (dmi_name_in_vendors("LENOVO"))" guard around it, but that >>>> seems unnecessary. >>> >>> Possibly just an update to the comment to make it clear that some >>> firmwares might legitimately set the flag? >> >> Ok, I've extended the comment above the override of the irq-flags with >> the following paragraph for v4 of this patch-set: >> >> * Note theoretically it is possible that some boards are not capable >> * of handling active low level interrupts. In that case setting the >> * flag to IRQF_TRIGGER_FALLING would not be a bug (and we would need >> * to work around this) but sofar all known usages of IRQF_TRIGGER_FALLING > > so far > >> * are a bug in the boards DSDT. > > board's > Thank you for the quick review, I've fixed both spelling errors for the upcoming v4. Regards, Hans From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E05D9C43333 for ; Wed, 20 Jan 2021 23:56:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A2B352360D for ; Wed, 20 Jan 2021 23:56:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404828AbhATX4W (ORCPT ); Wed, 20 Jan 2021 18:56:22 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:21732 "EHLO us-smtp-delivery-124.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730391AbhATVkE (ORCPT ); Wed, 20 Jan 2021 16:40:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611178702; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pHm8nVKL9Fr4wu0oxgE+9L7CgPJ7wuqXCFrUdbbeNXo=; b=M2u400wVsNoMJZvd/czGSJYiKff0cki5LJRmrwjqup9ydWdBl42VGB73awNGLd9bmTG2Jy d5QqMZoZcXvwKJR4dTA6/g93r2UR4r+Fv97oW2cgHe7ytXMZABAhzTzhRL2gz2Y6eS8WPv ldV2juBpqF6UcAOMwyvVNvYYQq0DrSY= Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-544-Z1F4ohL6MKu2iibntd3CHA-1; Wed, 20 Jan 2021 16:38:20 -0500 X-MC-Unique: Z1F4ohL6MKu2iibntd3CHA-1 Received: by mail-ed1-f69.google.com with SMTP id w4so30561edu.0 for ; Wed, 20 Jan 2021 13:38:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=pHm8nVKL9Fr4wu0oxgE+9L7CgPJ7wuqXCFrUdbbeNXo=; b=XeB6c+8fSG4PTD5WUYOP1eT2wPLV9Mx9rlI7b0DICxOcbbT0l9UbH1OgQidfcKb/y6 ZK9+Vp9ha7geMSUTu7R6EFn4H6wACFgY/85GdC3MZtQtrzCdRLf2mQNhxEqblORbQ7xc 0PWcwrej3dtqYJrdLFcD0qY77DwZuQBGjqo7LPTh/B+KkIzp6JunxIYjmDflDK70KiK5 HLal/YTEQ+qu+ojKP2ZczjBieDI0srMKdiwok7oPa+1ehoOFAgHoM/tyOO/RMyBbobog OKpAkPW3Ozz5cVoOoQRZL2zfoCCYx7VMFO5OQdXt0CGCY3T4BTlnwluMSuGXTomP15Z5 cl+A== X-Gm-Message-State: AOAM532qhc1lm7XqGAW8Df3cVqzSmFcjrYDByR/HeSfz9COwXm3JH4qP qjcw2SNXY8JEIpUNLFJjd4t1ZIDnj/dm/ejahmMs0mxGCMJ64YaLfXDibyWRsIe5Sogd9+GvUKH ziUH0WpQa/ue2aodhQ7VIJCq/ X-Received: by 2002:a05:6402:1c0b:: with SMTP id ck11mr8848945edb.35.1611178698931; Wed, 20 Jan 2021 13:38:18 -0800 (PST) X-Google-Smtp-Source: ABdhPJyC/ocWNIlZZBmymqhSrfoTNVxWmqEy5lrlXs0dgY1fwLV2Z2ltM1tFi4s7WBAkCG47K1QxnQ== X-Received: by 2002:a05:6402:1c0b:: with SMTP id ck11mr8848941edb.35.1611178698798; Wed, 20 Jan 2021 13:38:18 -0800 (PST) Received: from x1.localdomain (2001-1c00-0c1e-bf00-37a3-353b-be90-1238.cable.dynamic.v6.ziggo.nl. [2001:1c00:c1e:bf00:37a3:353b:be90:1238]) by smtp.gmail.com with ESMTPSA id z2sm1419474ejd.44.2021.01.20.13.38.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 Jan 2021 13:38:18 -0800 (PST) Subject: Re: [PATCH v3 3/5] mfd: arizona: Add support for ACPI enumeration of WM5102 connected over SPI To: Andy Shevchenko Cc: Mark Brown , Lee Jones , Cezary Rojewski , Pierre-Louis Bossart , Liam Girdwood , Jie Yang , patches@opensource.cirrus.com, Linux Kernel Mailing List , Charles Keepax , ALSA Development Mailing List , Christian Hartmann References: <20210117212252.206115-1-hdegoede@redhat.com> <20210117212252.206115-4-hdegoede@redhat.com> <20210118130227.GI4455@sirena.org.uk> <5ccf48f4-45dc-3a30-3d6a-cce066f01270@redhat.com> <20210118133449.GL4455@sirena.org.uk> From: Hans de Goede Message-ID: Date: Wed, 20 Jan 2021 22:38:17 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 1/20/21 8:59 PM, Andy Shevchenko wrote: > On Wed, Jan 20, 2021 at 9:18 PM Hans de Goede wrote: >> On 1/18/21 2:34 PM, Mark Brown wrote: >>> On Mon, Jan 18, 2021 at 02:13:50PM +0100, Hans de Goede wrote: >>> >>>> More in general I'm not aware of any (recent-ish) x86 GPIO controllers >>>> not being able to do active low interrupts. In theory we could hit this >>>> code path on ARM devices using ACPI enumeration, but I don't think it >>>> is likely we will see a combination of ARM + ACPI enumeration + >>>> WM5102 + GPIO controller not capable of active-low interrupts. >>> >>> I've not seen this issue on any ARM based systems. >>> >>>> This overriding of the flags definitely is necessary on the Lenovo >>>> devices in question. I could add a >>>> "if (dmi_name_in_vendors("LENOVO"))" guard around it, but that >>>> seems unnecessary. >>> >>> Possibly just an update to the comment to make it clear that some >>> firmwares might legitimately set the flag? >> >> Ok, I've extended the comment above the override of the irq-flags with >> the following paragraph for v4 of this patch-set: >> >> * Note theoretically it is possible that some boards are not capable >> * of handling active low level interrupts. In that case setting the >> * flag to IRQF_TRIGGER_FALLING would not be a bug (and we would need >> * to work around this) but sofar all known usages of IRQF_TRIGGER_FALLING > > so far > >> * are a bug in the boards DSDT. > > board's > Thank you for the quick review, I've fixed both spelling errors for the upcoming v4. Regards, Hans