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envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/10/2026 11:39 AM, TANG Tiancheng wrote: > Reset enters M-mode without clearing virt_enabled, leaving an invalid > M-mode, V=1 state after a reset from virtual mode. Clear virt_enabled > alongside the privilege reset. > This one is quite old. Fixes: dc5bd18fa5 ("RISC-V CPU Core Definition") > Signed-off-by: TANG Tiancheng > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 5fff9d745e9b36d9cbd30f166ec91b5165e5f497..f60d7cca1e2f0008b09b1055c5cdeed3ec4ad1d3 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -980,6 +980,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) > #ifndef CONFIG_USER_ONLY > env->misa_mxl = mcc->def->misa_mxl_max; > env->priv = PRV_M; > + env->virt_enabled = false; > env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); > if (env->misa_mxl > MXL_RV32) { > /* >