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Fri, 21 Aug 2026 10:32:45 -0700 (PDT) Received: from [172.20.6.168] ([108.174.179.84]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-395c4b47ae8sm4014181a91.13.2026.08.21.10.32.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Aug 2026 10:32:44 -0700 (PDT) Message-ID: Date: Fri, 21 Aug 2026 10:32:42 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] virtio: Add aligned ld/st accessors for vring To: Peter Maydell , BillXiang Cc: mst@redhat.com, pbonzini@redhat.com, peterx@redhat.com, philmd@mailo.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20260821100856.1794011-1-xiangwencheng@lanxincomputing.com> From: Richard Henderson Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 8/21/26 03:25, Peter Maydell wrote: > I'm tempted to suggest some kind of "if pointer is aligned take > aligned path, otherwise take slow path" either here or actually > in lduw_le_p(), but maybe that's a bad idea. Richard ? > > (I have a suspicion that other places than this one will assume > that an aligned ldl_he_p() is not going to tear.) I agree -- I expect most everything assumes ldl_he_p won't tear for aligned accesses. This kinda begs the question of what atomicity the caller expects. It's not implausible that an x86 path expects even unaligned accesses not crossing a cacheline to be atomic, since that's been a thing since 1995. I expect both IBM architectures similarly expect atomicity by alignment, since that's been a thing for s390 since yonks and Power has the same language. We have a bunch of code in accel/tcg/ldst_atomicity.c.inc that can handle this, we'd just need to provide it with the correct inputs. And I assume we'd still like to inline the single access on appropriate hosts. r~