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charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.3 (3.46.3-1.fc37) MIME-Version: 1.0 On Fri, 2023-01-20 at 15:54 +0000, Andrew Cooper wrote: > On 20/01/2023 2:59 pm, Oleksii Kurochko wrote: > > diff --git a/xen/arch/riscv/include/asm/processor.h > > b/xen/arch/riscv/include/asm/processor.h > > new file mode 100644 > > index 0000000000..5898a09ce6 > > --- /dev/null > > +++ b/xen/arch/riscv/include/asm/processor.h > > @@ -0,0 +1,114 @@ > > +/* SPDX-License-Identifier: MIT */ > > +/***************************************************************** > > ************* > > + * > > + * Copyright 2019 (C) Alistair Francis > > + * Copyright 2021 (C) Bobby Eshleman > > + * Copyright 2023 (C) Vates > > + * > > + */ > > + > > +#ifndef _ASM_RISCV_PROCESSOR_H > > +#define _ASM_RISCV_PROCESSOR_H > > + > > +#include > > + > > +#define RISCV_CPU_USER_REGS_zero=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 0 > > +#define RISCV_CPU_USER_REGS_ra=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 1 > > +#define RISCV_CPU_USER_REGS_sp=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 2 > > +#define RISCV_CPU_USER_REGS_gp=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 3 > > +#define RISCV_CPU_USER_REGS_tp=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 4 > > +#define RISCV_CPU_USER_REGS_t0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 5 > > +#define RISCV_CPU_USER_REGS_t1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 6 > > +#define RISCV_CPU_USER_REGS_t2=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 7 > > +#define RISCV_CPU_USER_REGS_s0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 8 > > +#define RISCV_CPU_USER_REGS_s1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 9 > > +#define RISCV_CPU_USER_REGS_a0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 10 > > +#define RISCV_CPU_USER_REGS_a1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 11 > > +#define RISCV_CPU_USER_REGS_a2=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 12 > > +#define RISCV_CPU_USER_REGS_a3=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 13 > > +#define RISCV_CPU_USER_REGS_a4=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 14 > > +#define RISCV_CPU_USER_REGS_a5=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 15 > > +#define RISCV_CPU_USER_REGS_a6=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 16 > > +#define RISCV_CPU_USER_REGS_a7=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 17 > > +#define RISCV_CPU_USER_REGS_s2=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 18 > > +#define RISCV_CPU_USER_REGS_s3=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 19 > > +#define RISCV_CPU_USER_REGS_s4=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 20 > > +#define RISCV_CPU_USER_REGS_s5=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 21 > > +#define RISCV_CPU_USER_REGS_s6=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 22 > > +#define RISCV_CPU_USER_REGS_s7=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 23 > > +#define RISCV_CPU_USER_REGS_s8=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 24 > > +#define RISCV_CPU_USER_REGS_s9=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 25 > > +#define RISCV_CPU_USER_REGS_s10=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 26 > > +#define RISCV_CPU_USER_REGS_s11=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 27 > > +#define RISCV_CPU_USER_REGS_t3=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 28 > > +#define RISCV_CPU_USER_REGS_t4=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 29 > > +#define RISCV_CPU_USER_REGS_t5=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 30 > > +#define RISCV_CPU_USER_REGS_t6=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 31 > > +#define RISCV_CPU_USER_REGS_sepc=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 32 > > +#define RISCV_CPU_USER_REGS_sstatus=C2=A0=C2=A0=C2=A0=C2=A0 33 > > +#define RISCV_CPU_USER_REGS_pregs=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = 34 > > +#define RISCV_CPU_USER_REGS_last=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 35 >=20 > This block wants moving into the asm-offsets infrastructure, but I > suspect they won't want to survive in this form. >=20 > edit: yeah, definitely not this form.=C2=A0 RISCV_CPU_USER_REGS_OFFSET is > a > recipe for bugs. >=20 Thanks for the recommendation I'll take it into account during a work on new version of the patch series. > > + > > +#define RISCV_CPU_USER_REGS_OFFSET(x)=C2=A0=C2=A0 ((RISCV_CPU_USER_REG= S_##x) > > * __SIZEOF_POINTER__) > > +#define RISCV_CPU_USER_REGS_SIZE=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 > > RISCV_CPU_USER_REGS_OFFSET(last) > > + > > +#ifndef __ASSEMBLY__ > > + > > +/* On stack VCPU state */ > > +struct cpu_user_regs > > +{ > > +=C2=A0=C2=A0=C2=A0 register_t zero; >=20 > unsigned long. Why is it better to define them as \unsigned long' instead of register_t? >=20 > > +=C2=A0=C2=A0=C2=A0 register_t ra; > > +=C2=A0=C2=A0=C2=A0 register_t sp; > > +=C2=A0=C2=A0=C2=A0 register_t gp; > > +=C2=A0=C2=A0=C2=A0 register_t tp; > > +=C2=A0=C2=A0=C2=A0 register_t t0; > > +=C2=A0=C2=A0=C2=A0 register_t t1; > > +=C2=A0=C2=A0=C2=A0 register_t t2; > > +=C2=A0=C2=A0=C2=A0 register_t s0; > > +=C2=A0=C2=A0=C2=A0 register_t s1; > > +=C2=A0=C2=A0=C2=A0 register_t a0; > > +=C2=A0=C2=A0=C2=A0 register_t a1; > > +=C2=A0=C2=A0=C2=A0 register_t a2; > > +=C2=A0=C2=A0=C2=A0 register_t a3; > > +=C2=A0=C2=A0=C2=A0 register_t a4; > > +=C2=A0=C2=A0=C2=A0 register_t a5; > > +=C2=A0=C2=A0=C2=A0 register_t a6; > > +=C2=A0=C2=A0=C2=A0 register_t a7; > > +=C2=A0=C2=A0=C2=A0 register_t s2; > > +=C2=A0=C2=A0=C2=A0 register_t s3; > > +=C2=A0=C2=A0=C2=A0 register_t s4; > > +=C2=A0=C2=A0=C2=A0 register_t s5; > > +=C2=A0=C2=A0=C2=A0 register_t s6; > > +=C2=A0=C2=A0=C2=A0 register_t s7; > > +=C2=A0=C2=A0=C2=A0 register_t s8; > > +=C2=A0=C2=A0=C2=A0 register_t s9; > > +=C2=A0=C2=A0=C2=A0 register_t s10; > > +=C2=A0=C2=A0=C2=A0 register_t s11; > > +=C2=A0=C2=A0=C2=A0 register_t t3; > > +=C2=A0=C2=A0=C2=A0 register_t t4; > > +=C2=A0=C2=A0=C2=A0 register_t t5; > > +=C2=A0=C2=A0=C2=A0 register_t t6; > > +=C2=A0=C2=A0=C2=A0 register_t sepc; > > +=C2=A0=C2=A0=C2=A0 register_t sstatus; > > +=C2=A0=C2=A0=C2=A0 /* pointer to previous stack_cpu_regs */ > > +=C2=A0=C2=A0=C2=A0 register_t pregs; >=20 > Stale comment?=C2=A0 Also, surely this wants to be cpu_user_regs *pregs; = ? >=20 Not really. Later it would be introduced another one structure: struct pcpu_info { ... struct cpu_user_regs *stack_cpu_regs; ... }; And stack_cpu_regs will be updated during context saving before jump to __handle_exception: /* new_stack_cpu_regs.pregs =3D old_stack_cpu_res */ REG_L t0, RISCV_PCPUINFO_OFFSET(stack_cpu_regs)(tp) REG_S t0, RISCV_CPU_USER_REGS_OFFSET(pregs)(sp) /* Update stack_cpu_regs */ REG_S sp, RISCV_PCPUINFO_OFFSET(stack_cpu_regs)(tp) And I skipped this part as pcpu_info isn't used anywhere now but reserve some place for pregs in advance. > > +}; > > + > > +static inline void wait_for_interrupt(void) >=20 > There's no point writing out the name in longhand for a wrapper > around a > single instruction. >=20 Will change it to "... wfi(void)" > ~Andrew