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GCGbGXC0r2wVWlYIm2kppE28ELqh/N/B5QbleOhqKrboHvjXvI9m2u/4p5Wcx0wAa+BoCLiq1K2 d+aneZepPdf8LZquH+yniZ7/v6O3j0D75vsKKt048bdvp63fdBMwkN/5Q6wzLA9KTv7XEHPWWW5 MRnPRgeCvEBIBeK1YSqoVP8S+FWjX/IYktb57PqDlV+VVw37luKJIPVsrgHZpgYOAAAPh+AhOEF qCrIjB8G8s3ADltNX1WEnpPTLDRzWLo94xvtAaJVVVKE3LFh6XItH54CPsPlN+HO/6aoSlCsSBT EpS3PIL8o6Mm0HbkQygEnxEKXVxriRZPP+l12ShE= Hi Greg/Sasha, On 13/10/26 5:07 pm, Greg Kroah-Hartman wrote: > 6.12-stable review patch. If anyone has any objections, please let me know. > > ------------------ > > From: Bartosz Golaszewski > > [ Upstream commit 6e0022b5ae3dc5b833af0fcc1578dc20a1d6bc71 ] > > aqr_gen1_read_status() decodes the MDIO_PHYXS_VEND_IF_STATUS register > to determine which SerDes interface the PHY is currently using on its > system side and stores the result in phydev->interface. phylink relies > on this value to configure the MAC. > > The autoneg == AUTONEG_DISABLE check is not correct: > MDIO_PHYXS_VEND_IF_STATUS is set by the PHY firmware based on the > negotiated link speed, not based on whether autoneg was used to reach > it. When the link comes up at 1G in forced mode, the register correctly > reads SGMII, but the early return prevents phydev->interface from being > updated. It stays at whatever value it held before (typically 2500BASE-X > from the initial autoneg run), so phylink configures the MAC for the > wrong interface and the link cannot come up. > > Remove the autoneg guard so that the system interface type is always > decoded when the link is up. > > Cc: stable@vger.kernel.org > Fixes: 110a2432c520 ("net: phy: aquantia: add downshift support") > Signed-off-by: Bartosz Golaszewski > Link: https://patch.msgid.link/20260923-qcom-sa8255p-emac-v15-1-e82f33720737@oss.qualcomm.com > Signed-off-by: Paolo Abeni > [ sashal: Adapted aqr_gen1_read_status() changes to aqr107_read_status() and its direct interface-assignment switch. ] > Signed-off-by: Sasha Levin > --- > drivers/net/phy/aquantia/aquantia_main.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/phy/aquantia/aquantia_main.c b/drivers/net/phy/aquantia/aquantia_main.c > index c33a5ef34ba03..0bf54723e3a1d 100644 > --- a/drivers/net/phy/aquantia/aquantia_main.c > +++ b/drivers/net/phy/aquantia/aquantia_main.c > @@ -339,7 +339,7 @@ static int aqr107_read_status(struct phy_device *phydev) > if (ret) > return ret; > > - if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) > + if (!phydev->link) > return 0; > > val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); > @@ -376,6 +376,9 @@ static int aqr107_read_status(struct phy_device *phydev) > break; > } > > + if (phydev->autoneg == AUTONEG_DISABLE) > + return 0; > + An AI-assisted review flagged missing interface-status protection in original 6.12.113-rc1 patch 264, 916768c55093. I verified the difference against upstream and the 6.12.y tip f4ffa8dc360b. Downstream aqr107_read_status() reads once, then handles OFF as default: default: phydev->interface = PHY_INTERFACE_MODE_NA; break; } if (phydev->autoneg == AUTONEG_DISABLE) return 0; Upstream aqr_gen1_read_status() polls before decoding; at 6e0022b5ae3d and current 0fcb05b72344 it also clears link: case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF: default: phydev->link = false; interface = PHY_INTERFACE_MODE_NA; break; When line-side link is up while the system interface still reads OFF, downstream publishes link-up with NA; phylink can configure MAC/PCS from that state. The patch newly exposes forced mode to this pre-existing autonegotiated-mode timing defect. 7e5b547cac7a ("net: phy: aquantia: poll status register") supplies the upstream protection. Should we backport that first ? thanks, Harshit> /* Read possibly downshifted rate from vendor register */ > return aqr107_read_rate(phydev); > }