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Thu, 07 Mar 2024 09:14:11 -0800 (PST) Message-ID: Date: Thu, 7 Mar 2024 18:14:09 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 12/23] xen/riscv: introduce io.h Content-Language: en-US To: Oleksii Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Julien Grall , Stefano Stabellini , Wei Liu , xen-devel@lists.xenproject.org References: <807c31d5-0c5a-4646-ba90-2f284289069f@suse.com> <2a3e49bf94332c17b50e4f0f745e4b28b16dceb1.camel@gmail.com> <2a05c233-b3c5-417c-bd6b-8b1c21f03c3d@suse.com> From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 07.03.2024 17:21, Oleksii wrote: > On Thu, 2024-03-07 at 16:32 +0100, Jan Beulich wrote: >> On 07.03.2024 14:44, Oleksii wrote: >>> On Thu, 2024-03-07 at 14:24 +0100, Jan Beulich wrote: >>>> On 07.03.2024 14:01, Oleksii wrote: >>>>> On Wed, 2024-03-06 at 15:13 +0100, Jan Beulich wrote: >>>>>>> +/* Generic IO read/write.  These perform native-endian >>>>>>> accesses. >>>>>>> */ >>>>>>> +static inline void __raw_writeb(uint8_t val, volatile void >>>>>>> __iomem >>>>>>> *addr) >>>>>>> +{ >>>>>>> +    asm volatile ( "sb %0, 0(%1)" : : "r" (val), "r" >>>>>>> (addr) ); >>>>>>> +} >>>>>> >>>>>> I realize this is like Linux has it, but how is the compiler >>>>>> to >>>>>> know >>>>>> that >>>>>> *addr is being access here?  >>>>> Assembler syntax told compiler that. 0(%1) - means that the >>>>> memory >>>>> location pointed to by the address in register %1. >>>> >>>> No, the compiler doesn't decompose the string to figure how >>>> operands >>>> are used. That's what the constraints are for. The only two >>>> things >>>> the >>>> compiler does with the string is replace % operators and count >>>> line >>>> separators. >>> It looks like I am missing something. >>> >>> addr -> a some register ( because of "r" contraint ). >>> val -> is also register ( because of "r" contraint ). >>> >>> So the compiler will update instert an instruction: >>>  sb reg1, 0(reg2) >>> >>> what means *(uint_8 *)reg2 = (uint8_t)reg1. >>> >>> What am I missing? >> >> The fact that the compiler will not know that *(uint_8 *)reg2 >> actually >> changes across this asm(). It may therefore continue to hold a cached >> value in a register, without knowing that its contents went stale. > Then it makes sense to me. Thanks. FTAOD similar considerations apply to memory reads. The compiler may need to know that values held in registers first need writing back to memory before an asm() can be invoked. > It explains why it is needed +Q, but > I don't understand why constraint 'o' isn't used for __raw_writew, but > was used for __raw_writeb: > > static inline void __raw_writeb(u8 val, volatile void __iomem *addr) > { > asm volatile("strb %1, %0" > : "+Qo" (*(volatile u8 __force *)addr) > : "r" (val)); > } > > static inline void __raw_writew(u16 val, volatile void __iomem *addr) > { > asm volatile("strh %1, %0" > : "+Q" (*(volatile u16 __force *)addr) > : "r" (val)); > } > > If I understand correctly 'o' that the address is offsettable, so why > addr can not be offsettable for everyone case? I don't know; there may be peculiarities in RISC-V specific constraints. > And one more thing, in Xen constraint "+" is used, but in Linux it was > dropped: > https://patchwork.kernel.org/project/linux-arm-kernel/patch/1426958753-26903-1-git-send-email-peter@hurleysoftware.com/ > > To me it looks like constraints should be always "+Qo". For plain writes it should at least be "=Qo" then, yes. To me making those input operands on Arm can't have been quite right. Jan