From: Jan Beulich <jbeulich@suse.com>
To: "Sébastien Chaumat" <euidzero@gmail.com>,
"Juergen Gross" <jgross@suse.com>
Cc: xen-devel@lists.xenproject.org
Subject: Re: [BUG]i2c_hid_acpi broken with 4.17.2 on Framework Laptop 13 AMD
Date: Thu, 21 Dec 2023 13:40:19 +0100 [thread overview]
Message-ID: <bcbceba7-42ac-45be-80ab-e3dfe7741ec6@suse.com> (raw)
In-Reply-To: <CAKm-UmZVoUhidEV15Xk+J_XN5a2GsBqMbXL9wqdFdoAFf_u5AA@mail.gmail.com>
On 20.12.2023 17:34, Sébastien Chaumat wrote:
> Here are the patches I made to xen and linux kernel
> Plus dmesg (bare metal,xen) and "xl dmesg"
So the problem looks to be that pci_xen_initial_domain() results in
permanent setup of IRQ7, when there only "static" ACPI tables (in
particular source overrides in MADT) are consulted. The necessary
settings, however, are known only after _CRS for the device was
evaluated (and possibly _PRS followed by invocation of _SRS). All of
this happens before xen_register_gsi() is called. But that function's
call to xen_register_pirq() is short-circuited by the very first if()
in xen_register_pirq() when there was an earlier invocation. Hence
the (wrong) "edge" binding remains in place, as was established by
the earlier call here.
Jürgen, there's an interesting comment in xen_bind_pirq_gsi_to_irq(),
right before invoking irq_set_chip_and_handler_name(). Despite what
the comment says (according to my reading), the fasteoi one is _not_
used in all cases. Assuming there's a reason for this, it's not clear
to me whether updating the handler later on is a valid thing to do.
__irq_set_handler() being even an exported symbol suggests that might
be an option to use here. Then again merely updating the handler may
not be sufficient, seeing there are also e.g. IRQD_TRIGGER_MASK and
IRQD_LEVEL.
Sébastien, to prove the (still pretty weak) theory that the change in
handler is all that's needed to make things work in your case, could
you fiddle with pci_xen_initial_domain() to have it skip IRQ7? (That
of course won't be a proper solution, but ought to be okay for your
system.) The main weakness of the theory is that IRQ7 really isn't
very special in this regard - other PCI IRQs routed to the low 16
IO-APIC pins ought to have similar issues (from the log, on your
system this would be at least IRQ6 and IRQ10, except that they happen
to be edge/low, so fitting the ISA defaults); only IRQ16 and up would
work okay.
Furthermore it might be interesting to know whether ELCR would give us
any hint in this case. Sadly depending on where you look,
applicability of this pair of registers (I/O ports 0x4d0 and 0x4d1)
to other than EISA systems is claimed true or false. Could you perhaps
make Xen simply log the values read from those two ports, by e.g.
inserting
printk("ELCR: %02x, %02x\n", inb(0x4d0), inb(0x4d1));
in, say, setup_dump_irqs()?
Jürgen, looking at pci_xen_initial_domain(), what's the purpose of
the loop in the final if()? Can this ever do anything useful when
the earlier comment suggests nr_legacy_irqs() is zero anyway? Or is
the comment simply inaccurate in not covering the "no IO-APICs" case?
Jan
next prev parent reply other threads:[~2023-12-21 12:40 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-03 9:56 [BUG]i2c_hid_acpi broken with 4.17.2 on Framework Laptop 13 AMD Sébastien Chaumat
2023-12-04 9:06 ` Jan Beulich
2023-12-04 19:17 ` Sébastien Chaumat
2023-12-05 8:17 ` Jan Beulich
2023-12-05 8:50 ` Sébastien Chaumat
2023-12-05 9:26 ` Sébastien Chaumat
2023-12-05 14:14 ` Sébastien Chaumat
2023-12-05 14:18 ` Jan Beulich
2023-12-05 16:19 ` Sébastien Chaumat
2023-12-05 20:31 ` Sébastien Chaumat
2023-12-06 7:15 ` Jan Beulich
2023-12-11 9:18 ` Sébastien Chaumat
2023-12-11 11:09 ` Sébastien Chaumat
2023-12-11 11:27 ` Jan Beulich
2023-12-11 14:17 ` Sébastien Chaumat
2023-12-11 14:21 ` Sébastien Chaumat
2023-12-18 16:21 ` Sébastien Chaumat
2023-12-18 16:44 ` Jan Beulich
2023-12-18 17:04 ` Sébastien Chaumat
2023-12-18 18:35 ` Sébastien Chaumat
2023-12-19 9:38 ` Jan Beulich
2023-12-19 13:15 ` Jan Beulich
2023-12-19 13:25 ` Jan Beulich
2023-12-19 15:15 ` Sébastien Chaumat
2023-12-19 19:03 ` Sébastien Chaumat
2023-12-19 23:06 ` Sébastien Chaumat
2023-12-19 23:11 ` Sébastien Chaumat
2023-12-19 23:50 ` Sébastien Chaumat
2023-12-20 0:23 ` Sébastien Chaumat
2023-12-20 10:06 ` Jan Beulich
2023-12-20 16:34 ` Sébastien Chaumat
2023-12-21 9:09 ` Jan Beulich
2023-12-21 12:40 ` Jan Beulich [this message]
2023-12-21 13:29 ` Juergen Gross
2023-12-21 15:22 ` Jan Beulich
2023-12-21 20:41 ` Sébastien Chaumat
2023-12-22 8:46 ` Jan Beulich
[not found] ` <CAKm-UmY126AfdGhWcZ3s9vwN9+ksVRRFEhOu0ZFMoDvxrqOibw@mail.gmail.com>
2023-12-22 14:38 ` Sébastien Chaumat
2023-12-27 10:20 ` Sébastien Chaumat
2023-12-27 11:43 ` Sébastien Chaumat
2024-01-02 20:23 ` Sébastien Chaumat
2024-01-16 15:52 ` Sébastien Chaumat
2024-01-16 16:18 ` Jan Beulich
2024-01-17 2:15 ` Mario Limonciello
2024-01-22 17:06 ` Sébastien Chaumat
2024-01-22 20:59 ` Mario Limonciello
2024-02-01 12:30 ` Sébastien Chaumat
2024-02-01 16:51 ` Sébastien Chaumat
2024-02-06 16:04 ` Sébastien Chaumat
2024-03-06 17:28 ` Sébastien Chaumat
2024-03-06 17:33 ` Mario Limonciello
2024-03-06 18:05 ` Sébastien Chaumat
2024-03-06 18:08 ` Mario Limonciello
2024-03-06 18:49 ` Sébastien Chaumat
2024-03-06 18:51 ` Mario Limonciello
2024-03-06 20:34 ` Sébastien Chaumat
2024-03-06 20:37 ` Mario Limonciello
2024-03-06 21:31 ` Marek Marczykowski-Górecki
2024-03-06 22:04 ` Mario Limonciello
2024-03-07 8:39 ` Jan Beulich
2024-03-08 9:55 ` Sébastien Chaumat
2024-10-10 14:45 ` David Woodhouse
2023-12-19 13:33 ` Jan Beulich
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