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Wed, 11 Jun 2025 08:12:29 -0700 (PDT) Received: from [192.168.1.3] ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a5324520e7sm15619819f8f.84.2025.06.11.08.12.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Jun 2025 08:12:29 -0700 (PDT) Message-ID: Date: Wed, 11 Jun 2025 16:12:28 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] perf: arm_spe: Relax period restriction To: Leo Yan , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org References: <20250528132501.129586-1-leo.yan@arm.com> Content-Language: en-US From: James Clark In-Reply-To: <20250528132501.129586-1-leo.yan@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250611_161235_052086_023688E9 X-CRM114-Status: GOOD ( 21.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 28/05/2025 2:25 pm, Leo Yan wrote: > The minimum interval specified the PMSIDR_EL1.Interval field is a > hardware recommendation. However, this value is set by hardware designer > before the production. It may not accurately reflects actual hardware > limitations, and tools currently have no way to test shorter periods. > > This change relaxes the limitation by allowing any non-zero periods. > This gives chance for experimenting smaller periods. > > The downside is that small periods may increase the risk of AUX ring > buffer overruns. When an overrun occurs, the perf core layer will > trigger an irq work to disable the event and wake up the tool in user > space to read the trace data. After the tool finishes reading, it will > re-enable the AUX event. > > Signed-off-by: Leo Yan > --- > > Changes from v1: > - Shifted bits with FIELD_PREP(). > - Removed warning log which is not quite useful. (James Clark) > > drivers/perf/arm_spe_pmu.c | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c > index 3efed8839a4e..e40e5daa838d 100644 > --- a/drivers/perf/arm_spe_pmu.c > +++ b/drivers/perf/arm_spe_pmu.c > @@ -308,12 +308,16 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) > > static void arm_spe_event_sanitise_period(struct perf_event *event) > { > - struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); > u64 period = event->hw.sample_period; > u64 max_period = PMSIRR_EL1_INTERVAL_MASK; > > - if (period < spe_pmu->min_period) > - period = spe_pmu->min_period; > + /* > + * As per the Arm ARM (DDI 0487 L.a), section D24.7.12 PMSIRR_EL1, > + * Sampling Interval Reload Register, the INTERVAL field (bits [31:8]) > + * states: "Software must set this to a nonzero value." > + */ > + if (period < FIELD_PREP(PMSIRR_EL1_INTERVAL_MASK, 1)) > + period = FIELD_PREP(PMSIRR_EL1_INTERVAL_MASK, 1); > else if (period > max_period) > period = max_period; > else Reviewed-by: James Clark