From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v5 1/9] drm/i915/display: Add new member to configure PCON color conversion
Date: Tue, 15 Nov 2022 13:18:03 +0530 [thread overview]
Message-ID: <bd38a962-381b-b31f-8a58-7be003b808ae@intel.com> (raw)
In-Reply-To: <Y21hPPewENMIzCpk@intel.com>
On 11/11/2022 2:08 AM, Ville Syrjälä wrote:
> On Fri, Oct 28, 2022 at 03:14:03PM +0530, Ankit Nautiyal wrote:
>> The decision to use DFP output format conversion capabilities should be
>> during compute_config phase.
>>
>> This patch adds new member to crtc_state to represent the final
>> output_format to the sink. In case of a DFP this can be different than
>> the output_format, as per the format conversion done via the PCON.
>>
>> This will help to store only the format conversion capabilities of the
>> DP device in intel_dp->dfp, and use crtc_state to compute and store the
>> configuration for color/format conversion for a given mode.
>>
>> v2: modified the new member to crtc_state to represent the final
>> output_format that eaches the sink, after possible conversion by
>> PCON kind of devices. (Ville)
>>
>> v3: Addressed comments from Ville:
>> -Added comments to clarify difference between sink_format and
>> output_format.
>> -Corrected the order of setting sink_format and output_format.
>> -Added readout for sink_format in get_pipe_config hooks.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
>> drivers/gpu/drm/i915/display/intel_crt.c | 1 +
>> .../drm/i915/display/intel_crtc_state_dump.c | 5 +--
>> drivers/gpu/drm/i915/display/intel_display.c | 5 +++
>> .../drm/i915/display/intel_display_types.h | 11 +++++-
>> drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++------
>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
>> drivers/gpu/drm/i915/display/intel_dvo.c | 1 +
>> drivers/gpu/drm/i915/display/intel_hdmi.c | 24 ++++++++-----
>> drivers/gpu/drm/i915/display/intel_lvds.c | 1 +
>> drivers/gpu/drm/i915/display/intel_tv.c | 1 +
>> drivers/gpu/drm/i915/display/vlv_dsi.c | 1 +
> We seem to miss intel_sdvo.c here. Apart from that looks nice.
>
> With sdvo fixed
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Thanks Ville. Will add sdvo in the next version of the patch.
Regards,
Ankit
>
>> 12 files changed, 63 insertions(+), 23 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>> index e05e7cd6c412..533563e94f58 100644
>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> @@ -1666,6 +1666,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
>> &pipe_config->hw.adjusted_mode;
>> int ret;
>>
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>
>> ret = intel_panel_compute_config(intel_connector, adjusted_mode);
>> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
>> index 94d0a5e1dd03..1b46d10fc6f4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_crt.c
>> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
>> @@ -391,6 +391,7 @@ static int intel_crt_compute_config(struct intel_encoder *encoder,
>> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
>> return -EINVAL;
>>
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>
>> return 0;
>> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> index e9212f69c360..ed427b9cbf09 100644
>> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> @@ -163,10 +163,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>>
>> snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
>> drm_dbg_kms(&i915->drm,
>> - "active: %s, output_types: %s (0x%x), output format: %s\n",
>> + "active: %s, output_types: %s (0x%x), output format: %s, sink format: %s\n",
>> str_yes_no(pipe_config->hw.active),
>> buf, pipe_config->output_types,
>> - output_formats(pipe_config->output_format));
>> + output_formats(pipe_config->output_format),
>> + output_formats(pipe_config->sink_format));
>>
>> drm_dbg_kms(&i915->drm,
>> "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 9697179309c4..6edb3f2af376 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -3240,6 +3240,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>> return false;
>>
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>> + pipe_config->sink_format = pipe_config->output_format;
>> pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
>> pipe_config->shared_dpll = NULL;
>>
>> @@ -3699,6 +3700,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
>> break;
>> }
>>
>> + pipe_config->sink_format = pipe_config->output_format;
>> +
>> pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
>>
>> pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
>> @@ -4094,6 +4097,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>> bdw_get_pipemisc_output_format(crtc);
>> }
>>
>> + pipe_config->sink_format = pipe_config->output_format;
>> +
>> pipe_config->gamma_mode = intel_de_read(dev_priv,
>> GAMMA_MODE(crtc->pipe));
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 609eeb5c7b71..924b7b656097 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1254,9 +1254,18 @@ struct intel_crtc_state {
>> /* HDMI High TMDS char rate ratio */
>> bool hdmi_high_tmds_clock_ratio;
>>
>> - /* Output format RGB/YCBCR etc */
>> + /*
>> + * Output format RGB/YCBCR etc., that is coming out
>> + * at the end of the pipe.
>> + */
>> enum intel_output_format output_format;
>>
>> + /*
>> + * Sink output format RGB/YCBCR etc., that is going
>> + * into the sink.
>> + */
>> + enum intel_output_format sink_format;
>> +
>> /* enable pipe gamma? */
>> bool gamma_enable;
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 7400d6b4c587..0e4f7b467970 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -787,11 +787,12 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
>>
>> static enum intel_output_format
>> intel_dp_output_format(struct intel_connector *connector,
>> - bool ycbcr_420_output)
>> + enum intel_output_format sink_format)
>> {
>> struct intel_dp *intel_dp = intel_attached_dp(connector);
>>
>> - if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
>> + if (!connector->base.ycbcr_420_allowed ||
>> + sink_format != INTEL_OUTPUT_FORMAT_YCBCR420)
>> return INTEL_OUTPUT_FORMAT_RGB;
>>
>> if (intel_dp->dfp.rgb_to_ycbcr &&
>> @@ -830,8 +831,14 @@ intel_dp_mode_min_output_bpp(struct intel_connector *connector,
>> const struct drm_display_mode *mode)
>> {
>> const struct drm_display_info *info = &connector->base.display_info;
>> - enum intel_output_format output_format =
>> - intel_dp_output_format(connector, drm_mode_is_420_only(info, mode));
>> + enum intel_output_format output_format, sink_format;
>> +
>> + if (drm_mode_is_420_only(info, mode))
>> + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
>> + else
>> + sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> +
>> + output_format = intel_dp_output_format(connector, sink_format);
>>
>> return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
>> }
>> @@ -1984,23 +1991,28 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
>>
>> ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
>>
>> - crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
>> -
>> - if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
>> + if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
>> drm_dbg_kms(&i915->drm,
>> "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
>> - crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> + } else if (ycbcr_420_only) {
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
>> + } else {
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> }
>>
>> + crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
>> +
>> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
>> respect_downstream_limits);
>> if (ret) {
>> - if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
>> - !connector->base.ycbcr_420_allowed ||
>> + if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>> !drm_mode_is_420_also(info, adjusted_mode))
>> return ret;
>>
>> - crtc_state->output_format = intel_dp_output_format(connector, true);
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
>> + crtc_state->output_format = intel_dp_output_format(connector,
>> + crtc_state->sink_format);
>> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
>> respect_downstream_limits);
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> index cd4e61026d98..496795476213 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> @@ -147,6 +147,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
>> return -EINVAL;
>>
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->has_pch_encoder = false;
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
>> index 595087288922..8f5b5612cba8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
>> @@ -278,6 +278,7 @@ static int intel_dvo_compute_config(struct intel_encoder *encoder,
>> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
>> return -EINVAL;
>>
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>
>> return 0;
>> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> index 93519fb23d9d..bd802ce69174 100644
>> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> @@ -2191,9 +2191,10 @@ static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
>>
>> static enum intel_output_format
>> intel_hdmi_output_format(struct intel_connector *connector,
>> - bool ycbcr_420_output)
>> + enum intel_output_format sink_format)
>> {
>> - if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
>> + if (connector->base.ycbcr_420_allowed &&
>> + sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
>> return INTEL_OUTPUT_FORMAT_YCBCR420;
>> else
>> return INTEL_OUTPUT_FORMAT_RGB;
>> @@ -2211,22 +2212,27 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
>> bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
>> int ret;
>>
>> - crtc_state->output_format = intel_hdmi_output_format(connector, ycbcr_420_only);
>> -
>> - if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
>> + if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
>> drm_dbg_kms(&i915->drm,
>> "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
>> - crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> + } else if (ycbcr_420_only) {
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
>> + } else {
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> }
>>
>> + crtc_state->output_format = intel_hdmi_output_format(connector,
>> + crtc_state->sink_format);
>> ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
>> if (ret) {
>> - if (intel_hdmi_is_ycbcr420(crtc_state) ||
>> - !connector->base.ycbcr_420_allowed ||
>> + if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>> !drm_mode_is_420_also(info, adjusted_mode))
>> return ret;
>>
>> - crtc_state->output_format = intel_hdmi_output_format(connector, true);
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
>> + crtc_state->output_format = intel_hdmi_output_format(connector,
>> + crtc_state->sink_format);
>> ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
>> index 246787bbf5ef..6d98bc8789a7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
>> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
>> @@ -439,6 +439,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
>> pipe_config->pipe_bpp = lvds_bpp;
>> }
>>
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>
>> /*
>> diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
>> index cf7d5c1ab406..9fe1fdca8336 100644
>> --- a/drivers/gpu/drm/i915/display/intel_tv.c
>> +++ b/drivers/gpu/drm/i915/display/intel_tv.c
>> @@ -1204,6 +1204,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
>> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
>> return -EINVAL;
>>
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>
>> drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n");
>> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
>> index 5a741ea4505f..11d9691c78cf 100644
>> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
>> @@ -279,6 +279,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
>> int ret;
>>
>> drm_dbg_kms(&dev_priv->drm, "\n");
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>
>> ret = intel_panel_compute_config(intel_connector, adjusted_mode);
>> --
>> 2.25.1
next prev parent reply other threads:[~2022-11-15 7:48 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-28 9:44 [Intel-gfx] [PATCH v5 0/9] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
2022-10-28 9:44 ` [Intel-gfx] [PATCH v5 1/9] drm/i915/display: Add new member to configure PCON color conversion Ankit Nautiyal
2022-11-10 20:38 ` Ville Syrjälä
2022-11-15 7:48 ` Nautiyal, Ankit K [this message]
2022-10-28 9:44 ` [Intel-gfx] [PATCH v5 2/9] drm/i915/display: Add new member in intel_dp to store ycbcr420 passthrough cap Ankit Nautiyal
2022-10-28 9:44 ` [Intel-gfx] [PATCH v5 3/9] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format Ankit Nautiyal
2022-11-10 21:06 ` Ville Syrjälä
2022-11-15 6:53 ` Nautiyal, Ankit K
2022-11-15 11:00 ` Ville Syrjälä
2022-11-15 16:42 ` Nautiyal, Ankit K
2022-10-28 9:44 ` [Intel-gfx] [PATCH v5 4/9] drm/i915/display: Use sink_format instead of ycbcr420_output flag Ankit Nautiyal
2022-10-28 9:44 ` [Intel-gfx] [PATCH v5 5/9] drm/i915/display: Add helper function to check if sink_format is 420 Ankit Nautiyal
2022-10-28 9:44 ` [Intel-gfx] [PATCH v5 6/9] drm/i915/dp: Avoid DSC with output_format YCBC420 Ankit Nautiyal
2022-10-28 9:44 ` [Intel-gfx] [PATCH v5 7/9] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC Ankit Nautiyal
2022-10-28 9:44 ` [Intel-gfx] [PATCH v5 8/9] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP Ankit Nautiyal
2022-10-28 9:44 ` [Intel-gfx] [PATCH v5 9/9] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints Ankit Nautiyal
2022-10-28 11:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev5) Patchwork
2022-10-28 11:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-28 19:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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