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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a01cd6cd2bsm10750735e9.4.2026.09.30.08.08.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Sep 2026 08:08:11 -0700 (PDT) Message-ID: Date: Wed, 30 Sep 2026 17:08:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 16/26] target/arm/kvm: Apply SYSREG props to the final vcpu To: Khushit Shah Cc: "eric.auger.pro@gmail.com" , "qemu-devel@nongnu.org" , "qemu-arm@nongnu.org" , "kvmarm@lists.linux.dev" , "peter.maydell@linaro.org" , Shaju Abraham , "yangjinqian1@huawei.com" , "cohuck@redhat.com" , "richard.henderson@linaro.org" , "sebott@redhat.com" , "skolothumtho@nvidia.com" , "philmd@oss.qualcomm.com" , "maz@kernel.org" , "oliver.upton@linux.dev" , "pbonzini@redhat.com" , "armbru@redhat.com" , "berrange@redhat.com" , "abologna@redhat.com" , "jdenemar@redhat.com" References: <20260916144721.751810-1-eric.auger@redhat.com> <20260916144721.751810-17-eric.auger@redhat.com> <8F110441-6D38-4134-9196-76AFA021250F@nutanix.com> From: Eric Auger In-Reply-To: <8F110441-6D38-4134-9196-76AFA021250F@nutanix.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: tin2NyBGuZR5z243oHFU2tmwlinTa2ir7CMu2TSwmI0_1790780894 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.341, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Hi Khushit, On 9/28/26 12:44 PM, Khushit Shah wrote: > >> On 16 Sep 2026, at 8:15 PM, Eric Auger wrote: >> >> !-------------------------------------------------------------------| >> CAUTION: External Email >> >> |-------------------------------------------------------------------! >> >> SYSREG prop settings were recorded in a hashtable but they >> are not yet injected on guest. Iterate over all set fields and >> apply the new value through KVM_SET_ONE_REG. The new field >> value overrides the current observable vcpu register value. >> >> Signed-off-by: Eric Auger > With this, I suppose, what named models will do is directly write to > ID register state, As it also defines state which affects vCPU init flags also. That's not what I had in mind. I thought you would apply the SYSREG settings at the same time. As mentionned, I don't think those settings are meant to substitute to legacy composite options that affect vcpu init settings. Besides the principle of this preparatory series is that the props for writable ID reg fields are meant to be fully reusable for named vcpu models. Only props for non writable fields should be specific to named vcpu models as they do not make sense on host/max vcpu model > >> --- >> target/arm/kvm.c | 65 +++++++++++++++++++++++++++++++++++++++++ >> target/arm/trace-events | 1 + >> 2 files changed, 66 insertions(+) >> >> diff --git a/target/arm/kvm.c b/target/arm/kvm.c >> index 3ec2618cc1..ddf320d0e6 100644 >> --- a/target/arm/kvm.c >> +++ b/target/arm/kvm.c >> @@ -343,6 +343,9 @@ static ARM64SysRegField *get_field(int i, ARM64SysReg *reg) >> #define MAKE_IDREG_KEY(reg_idx, field_shift) \ >> (((uint64_t)(reg_idx) << 8) | ((uint64_t)(field_shift) & 0xFF)) >> >> +#define KEY_TO_REG_IDX(key) ((uint32_t)(((uint64_t)(key)) >> 8)) >> +#define KEY_TO_SHIFT(key) ((uint8_t)(((uint64_t)(key)) & 0xFF)) >> + >> static void set_sysreg_prop(Object *obj, Visitor *v, >> const char *name, void *opaque, >> Error **errp) >> @@ -2215,6 +2218,63 @@ int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) >> return 0; >> } >> >> +static int kvm_arm_apply_sysreg_props(ARMCPU *cpu, Error **errp) >> +{ >> + uint64_t *idregs = cpu->isar.idregs; >> + gpointer key_ptr, value_ptr; >> + CPUState *cs = CPU(cpu); >> + GHashTableIter iter; >> + >> + g_hash_table_iter_init(&iter, cpu->sysreg_props); >> + >> + while (g_hash_table_iter_next(&iter, &key_ptr, &value_ptr)) { >> + uint64_t key = (uint64_t)key_ptr; >> + uint64_t value = (uint64_t)value_ptr; >> + uint32_t reg_idx = KEY_TO_REG_IDX(key); >> + uint8_t lower = KEY_TO_SHIFT(key); >> + ARM64SysReg *reg = &arm64_id_regs[reg_idx]; >> + struct kvm_one_reg kvm_reg; >> + uint64_t current, old, mask; >> + uint64_t kvm_idx; >> + ARM64SysRegField *field = get_field(lower, reg); >> + int length = field->length; >> + uint64_t oldfv; >> + int ret; >> + >> + mask = MAKE_64BIT_MASK(lower, length); >> + value = value << lower; >> + >> + old = idregs[reg_idx]; >> + >> + kvm_idx = idregs_sysreg_to_kvm_reg(id_register_sysreg[reg_idx]); >> + ret = read_sys_reg64(cs->kvm_fd, ¤t, kvm_idx); >> + if (ret) { >> + error_setg(errp, "failed to read the current value of %s", >> + reg->name); >> + return ret; >> + } >> + oldfv = (current & mask) >> lower; >> + >> + idregs[reg_idx] = current & ~mask; >> + idregs[reg_idx] |= value; >> + kvm_reg.id = kvm_idx; >> + kvm_reg.addr = (uintptr_t)&idregs[reg_idx]; >> + > We can ignore this if value == old value sure, modified > >> + ret = ioctl(cs->kvm_fd, KVM_SET_ONE_REG, &kvm_reg); >> + if (ret) { >> + error_setg(errp, "failed to apply new value 0x%"PRIx64" for field %s.%s " >> + "(previous is 0x%"PRIx64"): %m", idregs[reg_idx], >> + reg->name, field->name, oldfv); >> + return ret; >> + } >> + >> + trace_apply_sysreg_prop(reg->name, field->name, old, current, >> + mask, value, idregs[reg_idx]); >> + } >> + return 0; >> +} >> + >> int kvm_arch_init_vcpu(CPUState *cs, Error **errp) >> { >> int ret; >> @@ -2315,6 +2375,11 @@ int kvm_arch_init_vcpu(CPUState *cs, Error **errp) >> } >> cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK; >> >> + ret = kvm_arm_apply_sysreg_props(cpu, errp); >> + if (ret) { >> + return ret; >> + } >> + > This should also happen on vCPU reset. On which path is it needed? on qmp system_reset I can see that the former values applied with SYSREG settings are kept. Thanks Eric > > Overall, I like this approach as if the user does not provide any property overrides, it should behave the same as older builds. > > Warm Regards, > Khushit >> return kvm_arm_init_cpreg_list(cpu); >> } >> >> diff --git a/target/arm/trace-events b/target/arm/trace-events >> index d72ad6b671..b4d2b45a7d 100644 >> --- a/target/arm/trace-events >> +++ b/target/arm/trace-events >> @@ -18,6 +18,7 @@ kvm_arm_writable_idregs_to_cpreg_list(const char *name, uint64_t previous, uint6 >> decode_idreg_writemap(const char* name, int lower, int upper, char *prop_name) "%s [%d:%d] is writable (prop %s)" >> get_sysreg_prop(const char *name, uint64_t value) "%s 0x%"PRIx64 >> set_sysreg_prop(const char *name, uint64_t old, uint64_t mask, uint64_t field_value, uint64_t new) "%s old reg value=0x%"PRIx64" mask=0x%"PRIx64" new field value=0x%"PRIx64" new reg value=0x%"PRIx64 >> +apply_sysreg_prop(const char *reg_name, const char *field_name, uint64_t old, uint64_t current, uint64_t mask, uint64_t field_value, uint64_t new) "%s.%s old=0x%"PRIx64" current=0x%"PRIx64" mask=0x%"PRIx64" new field value=0x%"PRIx64" new=0x%"PRIx64 >> nb_sysreg_props(const char *name, int count) "%s: %d SYSREG properties" >> >> # cpu.c >> -- >> 2.53.0 >>