From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, HTML_MESSAGE,INCLUDES_PATCH,MAILING_LIST_MULTI,MIME_HTML_MOSTLY,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D6A2C3F2D1 for ; Wed, 4 Mar 2020 17:14:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6D61F21775 for ; Wed, 4 Mar 2020 17:14:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6D61F21775 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 08A1E6EB44; Wed, 4 Mar 2020 17:14:44 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5D4476EB43 for ; Wed, 4 Mar 2020 17:14:42 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Mar 2020 09:14:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,514,1574150400"; d="scan'208,217";a="234179854" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by fmsmga008.fm.intel.com with ESMTP; 04 Mar 2020 09:14:40 -0800 Received: from irsmsx601.ger.corp.intel.com (163.33.146.7) by IRSMSX102.ger.corp.intel.com (163.33.3.155) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 4 Mar 2020 17:14:40 +0000 Received: from irsmsx604.ger.corp.intel.com (163.33.146.137) by irsmsx601.ger.corp.intel.com (163.33.146.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 4 Mar 2020 17:14:39 +0000 Received: from irsmsx604.ger.corp.intel.com ([163.33.146.137]) by IRSMSX604.ger.corp.intel.com ([163.33.146.137]) with mapi id 15.01.1713.004; Wed, 4 Mar 2020 17:14:39 +0000 From: "Lisovskiy, Stanislav" To: Ville Syrjala , "intel-gfx@lists.freedesktop.org" Thread-Topic: [PATCH v2 07/20] drm/i915: Unify the low level dbuf code Thread-Index: AQHV6/6uiGNLB8c1mE6/dzTFurMHp6g4ttgJ Date: Wed, 4 Mar 2020 17:14:39 +0000 Message-ID: References: <20200225171125.28885-1-ville.syrjala@linux.intel.com>, <20200225171125.28885-8-ville.syrjala@linux.intel.com> In-Reply-To: <20200225171125.28885-8-ville.syrjala@linux.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.253.164] MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH v2 07/20] drm/i915: Unify the low level dbuf code X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============0231376437==" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" --===============0231376437== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_bda3246008504c979c6322e7ff68e43dintelcom_" --_000_bda3246008504c979c6322e7ff68e43dintelcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable >- /* If 2nd DBuf slice required, enable it here */ > if (INTEL_GEN(dev_priv) >=3D 11 && slices_union !=3D hw_enabled_sl= ices) >- icl_dbuf_slices_update(dev_priv, slices_union); >+ gen9_dbuf_slices_update(dev_priv, slices_union); >} > static void icl_dbuf_slice_post_update(struct intel_atomic_state *state) >@@ -15307,9 +15306,8 @@ static void icl_dbuf_slice_post_update(struct inte= l_atomic_state *state) > u8 hw_enabled_slices =3D dev_priv->enabled_dbuf_slices_mask; > u8 required_slices =3D state->enabled_dbuf_slices_mask; >- /* If 2nd DBuf slice is no more required disable it */ > if (INTEL_GEN(dev_priv) >=3D 11 && required_slices !=3D hw_enable= d_slices) >- icl_dbuf_slices_update(dev_priv, required_slices); >+ gen9_dbuf_slices_update(dev_priv, required_slices); Doesn't make much sense. Just look - previously we were checking if INTEL_G= EN is >=3D than 11(which _is_ ICL) and now we still _do_ check if INTEL_GEN is >=3D 11, but... call now functi= on renamed to gen9 I guess you either need to change INTEL_GEN check to be >=3D9 to at least l= ook somewhat consistent or leave it as is. Or at least rename icl_ prefix to gen11_ otherwise that = looks inconsistent, i.e you are now checking that gen is >=3D 11 and then OK - now let's call gen 9= ! :) Stan ________________________________ From: Ville Syrjala Sent: Tuesday, February 25, 2020 7:11:12 PM To: intel-gfx@lists.freedesktop.org Cc: Lisovskiy, Stanislav Subject: [PATCH v2 07/20] drm/i915: Unify the low level dbuf code From: Ville Syrj=E4l=E4 The low level dbuf slice code is rather inconsitent with its functiona naming and organization. Make it more consistent. Also share the enable/disable functions between all platforms since the same code works just fine for all of them. Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrj=E4l=E4 --- drivers/gpu/drm/i915/display/intel_display.c | 6 +-- .../drm/i915/display/intel_display_power.c | 44 ++++++++----------- .../drm/i915/display/intel_display_power.h | 6 +-- 3 files changed, 24 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm= /i915/display/intel_display.c index 3031e64ee518..6952c398cc43 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15296,9 +15296,8 @@ static void icl_dbuf_slice_pre_update(struct intel_= atomic_state *state) u8 required_slices =3D state->enabled_dbuf_slices_mask; u8 slices_union =3D hw_enabled_slices | required_slices; - /* If 2nd DBuf slice required, enable it here */ if (INTEL_GEN(dev_priv) >=3D 11 && slices_union !=3D hw_enabled_sl= ices) - icl_dbuf_slices_update(dev_priv, slices_union); + gen9_dbuf_slices_update(dev_priv, slices_union); } static void icl_dbuf_slice_post_update(struct intel_atomic_state *state) @@ -15307,9 +15306,8 @@ static void icl_dbuf_slice_post_update(struct intel= _atomic_state *state) u8 hw_enabled_slices =3D dev_priv->enabled_dbuf_slices_mask; u8 required_slices =3D state->enabled_dbuf_slices_mask; - /* If 2nd DBuf slice is no more required disable it */ if (INTEL_GEN(dev_priv) >=3D 11 && required_slices !=3D hw_enabled= _slices) - icl_dbuf_slices_update(dev_priv, required_slices); + gen9_dbuf_slices_update(dev_priv, required_slices); } static void skl_commit_modeset_enables(struct intel_atomic_state *state) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/g= pu/drm/i915/display/intel_display_power.c index e81e561e8ac0..ce3bbc4c7a27 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4433,15 +4433,18 @@ static void intel_power_domains_sync_hw(struct drm_= i915_private *dev_priv) mutex_unlock(&power_domains->lock); } -static void intel_dbuf_slice_set(struct drm_i915_private *dev_priv, - enum dbuf_slice slice, bool enable) +static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv, + enum dbuf_slice slice, bool enable) { i915_reg_t reg =3D DBUF_CTL_S(slice); bool state; u32 val; val =3D intel_de_read(dev_priv, reg); - val =3D enable ? (val | DBUF_POWER_REQUEST) : (val & ~DBUF_POWER_RE= QUEST); + if (enable) + val |=3D DBUF_POWER_REQUEST; + else + val &=3D ~DBUF_POWER_REQUEST; intel_de_write(dev_priv, reg, val); intel_de_posting_read(dev_priv, reg); udelay(10); @@ -4452,18 +4455,8 @@ static void intel_dbuf_slice_set(struct drm_i915_pri= vate *dev_priv, slice, enable ? "enable" : "disable"); } -static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) -{ - icl_dbuf_slices_update(dev_priv, BIT(DBUF_S1)); -} - -static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) -{ - icl_dbuf_slices_update(dev_priv, 0); -} - -void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, - u8 req_slices) +void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, + u8 req_slices) { int num_slices =3D INTEL_INFO(dev_priv)->num_supported_dbuf_slices= ; struct i915_power_domains *power_domains =3D &dev_priv->power_doma= ins; @@ -4486,28 +4479,29 @@ void icl_dbuf_slices_update(struct drm_i915_private= *dev_priv, mutex_lock(&power_domains->lock); for (slice =3D DBUF_S1; slice < num_slices; slice++) - intel_dbuf_slice_set(dev_priv, slice, - req_slices & BIT(slice)); + gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice= )); dev_priv->enabled_dbuf_slices_mask =3D req_slices; mutex_unlock(&power_domains->lock); } -static void icl_dbuf_enable(struct drm_i915_private *dev_priv) +static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) { - skl_ddb_get_hw_state(dev_priv); + dev_priv->enabled_dbuf_slices_mask =3D + intel_enabled_dbuf_slices_mask(dev_priv); + /* * Just power up at least 1 slice, we will * figure out later which slices we have and what we need. */ - icl_dbuf_slices_update(dev_priv, dev_priv->enabled_dbuf_slices_mask= | - BIT(DBUF_S1)); + gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) | + dev_priv->enabled_dbuf_slices_mask); } -static void icl_dbuf_disable(struct drm_i915_private *dev_priv) +static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) { - icl_dbuf_slices_update(dev_priv, 0); + gen9_dbuf_slices_update(dev_priv, 0); } static void icl_mbus_init(struct drm_i915_private *dev_priv) @@ -5067,7 +5061,7 @@ static void icl_display_core_init(struct drm_i915_pri= vate *dev_priv, intel_cdclk_init_hw(dev_priv); /* 5. Enable DBUF. */ - icl_dbuf_enable(dev_priv); + gen9_dbuf_enable(dev_priv); /* 6. Setup MBUS. */ icl_mbus_init(dev_priv); @@ -5090,7 +5084,7 @@ static void icl_display_core_uninit(struct drm_i915_p= rivate *dev_priv) /* 1. Disable all display engine functions -> aready done */ /* 2. Disable DBUF */ - icl_dbuf_disable(dev_priv); + gen9_dbuf_disable(dev_priv); /* 3. Disable CD clock */ intel_cdclk_uninit_hw(dev_priv); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/g= pu/drm/i915/display/intel_display_power.h index 601e000ffd0d..1a275611241e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -312,13 +312,13 @@ enum dbuf_slice { DBUF_S2, }; +void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, + u8 req_slices); + #define with_intel_display_power(i915, domain, wf) \ for ((wf) =3D intel_display_power_get((i915), (domain)); (wf); \ intel_display_power_put_async((i915), (domain), (wf)), (wf) = =3D 0) -void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, - u8 req_slices); - void chv_phy_powergate_lanes(struct intel_encoder *encoder, bool override, unsigned int mask); bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy= phy, -- 2.24.1 --_000_bda3246008504c979c6322e7ff68e43dintelcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

>-       /* If 2nd= DBuf slice required, enable it here */
>        if (INTEL_GEN(dev_priv= ) >=3D 11 && slices_union !=3D hw_enabled_slices)
>-        &= nbsp;      icl_dbuf_slices_update(dev_priv, slices= _union);
>+       &nb= sp;       gen9_dbuf_slices_update(dev_priv, s= lices_union);
>}
 
> static void icl_dbuf_slice_post_update(struct int= el_atomic_state *state)
>@@ -15307,9 +15306,8 @@ static void icl_dbuf_s= lice_post_update(struct intel_atomic_state *state)
>        u8 hw_enabled_slices = =3D dev_priv->enabled_dbuf_slices_mask;
>        u8 required_slices =3D= state->enabled_dbuf_slices_mask;
 
>-       /* If 2nd DB= uf slice is no more required disable it */
>         if (INTEL_GEN(de= v_priv) >=3D 11 && required_slices !=3D hw_enabled_slices)
>-        &= nbsp;      icl_dbuf_slices_update(dev_priv, requir= ed_slices);
>+       &nb= sp;       gen9_dbuf_slices_update(dev_priv, r= equired_slices);


Doesn't make much sense. Just look - previously we = were checking if INTEL_GEN is >=3D than 11(which _is_ ICL)

and now we still _do_ check if INTEL_GEN is >=3D= 11, but... call now function renamed to gen9


I guess you either need to change INTEL_GEN check t= o be >=3D9 to at least look somewhat consistent

or leave it as is. Or at least rename icl_ prefix t= o gen11_ otherwise that looks inconsistent, i.e

you are now checking that gen is >=3D 11 and the= n OK - now let's call gen 9! :)


Stan
From: Ville Syrjala <v= ille.syrjala@linux.intel.com>
Sent: Tuesday, February 25, 2020 7:11:12 PM
To: intel-gfx@lists.freedesktop.org
Cc: Lisovskiy, Stanislav
Subject: [PATCH v2 07/20] drm/i915: Unify the low level dbuf code
 
From: Ville Syrj=E4l=E4 <ville.syrjala@linux.in= tel.com>

The low level dbuf slice code is rather inconsitent with its
functiona naming and organization. Make it more consistent.

Also share the enable/disable functions between all platforms
since the same code works just fine for all of them.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  6 +--<= br>  .../drm/i915/display/intel_display_power.c    | 44 = 3;+++++++-----------
 .../drm/i915/display/intel_display_power.h    |  = 6 +--
 3 files changed, 24 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm= /i915/display/intel_display.c
index 3031e64ee518..6952c398cc43 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15296,9 +15296,8 @@ static void icl_dbuf_slice_pre_update(struct in= tel_atomic_state *state)
         u8 required_slices =3D sta= te->enabled_dbuf_slices_mask;
         u8 slices_union =3D hw_ena= bled_slices | required_slices;
 
-       /* If 2nd DBuf slice required, enable= it here */
         if (INTEL_GEN(dev_priv) &g= t;=3D 11 && slices_union !=3D hw_enabled_slices)
-            &n= bsp;  icl_dbuf_slices_update(dev_priv, slices_union);
+           &nbs= p;   gen9_dbuf_slices_update(dev_priv, slices_union);
 }
 
 static void icl_dbuf_slice_post_update(struct intel_atomic_state *sta= te)
@@ -15307,9 +15306,8 @@ static void icl_dbuf_slice_post_update(struct i= ntel_atomic_state *state)
         u8 hw_enabled_slices =3D d= ev_priv->enabled_dbuf_slices_mask;
         u8 required_slices =3D sta= te->enabled_dbuf_slices_mask;
 
-       /* If 2nd DBuf slice is no more requi= red disable it */
         if (INTEL_GEN(dev_priv) &g= t;=3D 11 && required_slices !=3D hw_enabled_slices)
-            &n= bsp;  icl_dbuf_slices_update(dev_priv, required_slices);
+           &nbs= p;   gen9_dbuf_slices_update(dev_priv, required_slices);
 }
 
 static void skl_commit_modeset_enables(struct intel_atomic_state *sta= te)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/g= pu/drm/i915/display/intel_display_power.c
index e81e561e8ac0..ce3bbc4c7a27 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4433,15 +4433,18 @@ static void intel_power_domains_sync_hw(struct = drm_i915_private *dev_priv)
         mutex_unlock(&power_do= mains->lock);
 }
 
-static void intel_dbuf_slice_set(struct drm_i915_private *dev_priv,
-            &n= bsp;            = ;       enum dbuf_slice slice, bool enable) +static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
+           &nbs= p;            &= nbsp;      enum dbuf_slice slice, bool enable)
 {
         i915_reg_t reg =3D DBUF_CT= L_S(slice);
         bool state;
         u32 val;
 
         val =3D intel_de_read(dev_= priv, reg);
-       val =3D enable ? (val | DBUF_POWER_RE= QUEST) : (val & ~DBUF_POWER_REQUEST);
+       if (enable)
+           &nbs= p;   val |=3D DBUF_POWER_REQUEST;
+       else
+           &nbs= p;   val &=3D ~DBUF_POWER_REQUEST;
         intel_de_write(dev_priv, r= eg, val);
         intel_de_posting_read(dev_= priv, reg);
         udelay(10);
@@ -4452,18 +4455,8 @@ static void intel_dbuf_slice_set(struct drm_i915= _private *dev_priv,
            &nb= sp;     slice, enable ? "enable" : "disa= ble");
 }
 
-static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
-{
-       icl_dbuf_slices_update(dev_priv, BIT(= DBUF_S1));
-}
-
-static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
-{
-       icl_dbuf_slices_update(dev_priv, 0);<= br> -}
-
-void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
-            &n= bsp;            = ;  u8 req_slices)
+void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
+           &nbs= p;            &= nbsp;   u8 req_slices)
 {
         int num_slices =3D INTEL_I= NFO(dev_priv)->num_supported_dbuf_slices;
         struct i915_power_domains = *power_domains =3D &dev_priv->power_domains;
@@ -4486,28 +4479,29 @@ void icl_dbuf_slices_update(struct drm_i915_pri= vate *dev_priv,
         mutex_lock(&power_doma= ins->lock);
 
         for (slice =3D DBUF_S1; sl= ice < num_slices; slice++)
-            &n= bsp;  intel_dbuf_slice_set(dev_priv, slice,
-            &n= bsp;            = ;           req_slices &a= mp; BIT(slice));
+           &nbs= p;   gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(sl= ice));
 
         dev_priv->enabled_dbuf_= slices_mask =3D req_slices;
 
         mutex_unlock(&power_do= mains->lock);
 }
 
-static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
+static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
 {
-       skl_ddb_get_hw_state(dev_priv);
+       dev_priv->enabled_dbuf_slices_= mask =3D
+           &nbs= p;   intel_enabled_dbuf_slices_mask(dev_priv);
+
         /*
          * Just power up at l= east 1 slice, we will
          * figure out later w= hich slices we have and what we need.
          */
-       icl_dbuf_slices_update(dev_priv, dev_= priv->enabled_dbuf_slices_mask |
-            &n= bsp;            = ;     BIT(DBUF_S1));
+       gen9_dbuf_slices_update(dev_priv,= BIT(DBUF_S1) |
+           &nbs= p;            &= nbsp;      dev_priv->enabled_dbuf_slices_mask);=
 }
 
-static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
+static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
 {
-       icl_dbuf_slices_update(dev_priv, 0);<= br> +       gen9_dbuf_slices_update(dev_priv,= 0);
 }
 
 static void icl_mbus_init(struct drm_i915_private *dev_priv)
@@ -5067,7 +5061,7 @@ static void icl_display_core_init(struct drm_i915= _private *dev_priv,
         intel_cdclk_init_hw(dev_pr= iv);
 
         /* 5. Enable DBUF. */
-       icl_dbuf_enable(dev_priv);
+       gen9_dbuf_enable(dev_priv);
 
         /* 6. Setup MBUS. */
         icl_mbus_init(dev_priv); @@ -5090,7 +5084,7 @@ static void icl_display_core_uninit(struct drm_i9= 15_private *dev_priv)
         /* 1. Disable all display = engine functions -> aready done */
 
         /* 2. Disable DBUF */
-       icl_dbuf_disable(dev_priv);
+       gen9_dbuf_disable(dev_priv);
 
         /* 3. Disable CD clock */<= br>          intel_cdclk_uninit_hw(dev_= priv);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/g= pu/drm/i915/display/intel_display_power.h
index 601e000ffd0d..1a275611241e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -312,13 +312,13 @@ enum dbuf_slice {
         DBUF_S2,
 };
 
+void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
+           &nbs= p;            &= nbsp;   u8 req_slices);
+
 #define with_intel_display_power(i915, domain, wf) \
         for ((wf) =3D intel_displa= y_power_get((i915), (domain)); (wf); \
            &nb= sp; intel_display_power_put_async((i915), (domain), (wf)), (wf) =3D 0)
 
-void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
-            &n= bsp;            = ;  u8 req_slices);
-
 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
            &nb= sp;            =      bool override, unsigned int mask);
 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpi= o_phy phy,
--
2.24.1

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