From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 250A4C38A2D for ; Wed, 26 Oct 2022 16:45:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233718AbiJZQpM (ORCPT ); Wed, 26 Oct 2022 12:45:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233752AbiJZQpK (ORCPT ); Wed, 26 Oct 2022 12:45:10 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A835C2BB3B for ; Wed, 26 Oct 2022 09:45:08 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id b2so29867998lfp.6 for ; Wed, 26 Oct 2022 09:45:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=H7iGH0jCRRF8jnKlYa8LooBNl7HXW3ndfP8Ygj8/9LU=; b=f8mLasIcQlGNu1JsI61aP8xAvJi/H4LSgM4xG4q7FmrSVnWvTcFJ17XxWsMT2aK7r+ aFImRGqQi2XxCoB3pDtjZoEDXsSl1DBTTxSDfbzac5gyRQTitDY/2c45efNGdNm39FcH fUCDrxn83Xnp2fRjAuw4XDUCscF3tLRxaNjkyXqncjtu/JFirqiFUCspnJgD/yAUHs3p jU57MoaocCyU7mgNtwIDfHYkjkngRRs5AQm3aPtKIatiiOqaCJFiCAh7qIsvNIcgwYzh OnlK2TXdCeJU+3UiMR6bOX63Hs63z6z5T74Okeh0QJ4EcjiRlSsVk2ctkqsdjOK2YfZw Ut/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=H7iGH0jCRRF8jnKlYa8LooBNl7HXW3ndfP8Ygj8/9LU=; b=ix4RxqKbKyQhaK15BTPUn3QlC6eDAzasztihNI5tO1/dDy0vkUNNb2RBeRP+dC13Ll r4O0TBlU2vzRz0iyn+nYne8WcyTrVevjpJRzZbjW/vA0SDnqwvR0C+fotIaEaHJLpPOP 2FuOjtv7a11og6iT25UrPfy+eSgLyXb5db1qooprSB3uMAPr3D7y7GAJ9rHy7iM5Tp9a hfA3NpkFyZEmhqQ3r+8QeaQ+YS9vRO1fCcttDuaa7WJGm2MR7KPBm/H0BCKywOaOnmQA pbBf/y+jkV4m/DpZkpMDGqADu/zSGcEZX8Nif7KILe1ndKS8oOPqjczFprOv/7IEGKdo AC6Q== X-Gm-Message-State: ACrzQf3CdyLBxHYZhN9tFz1gPz2/SWCC4bfDd+DOim2XLLGdrdjf/Qe2 JUtiowWFq9RTbQAVC9hfxT14Cw== X-Google-Smtp-Source: AMsMyM7c5KMB9Ify6vaDssr65IJB+YQYn2ig8pKKgsff7SJZQMwMnQ5bROeYvaCFOGh8FFeaZW9hGg== X-Received: by 2002:a05:6512:2282:b0:4a2:7dc5:6630 with SMTP id f2-20020a056512228200b004a27dc56630mr16662394lfu.645.1666802706946; Wed, 26 Oct 2022 09:45:06 -0700 (PDT) Received: from [10.27.10.248] ([195.165.23.90]) by smtp.gmail.com with ESMTPSA id p6-20020a05651238c600b0049313f77755sm890178lft.213.2022.10.26.09.45.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Oct 2022 09:45:06 -0700 (PDT) Message-ID: Date: Wed, 26 Oct 2022 19:45:05 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.3 Subject: Re: [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers Content-Language: en-GB To: Manivannan Sadhasivam Cc: vkoul@kernel.org, andersson@kernel.org, kishon@ti.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org References: <20220910063857.17372-1-manivannan.sadhasivam@linaro.org> <20221026143152.GA93939@thinkpad> From: Dmitry Baryshkov In-Reply-To: <20221026143152.GA93939@thinkpad> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 26/10/2022 17:31, Manivannan Sadhasivam wrote: > On Wed, Sep 21, 2022 at 04:06:10PM +0300, Dmitry Baryshkov wrote: >> On 10/09/2022 09:38, Manivannan Sadhasivam wrote: >>> In the PCS region, registers QPHY_V5_PCS_EQ_CONFIG4 and >>> QPHY_V5_PCS_EQ_CONFIG5 should be used instead of QPHY_V5_PCS_EQ_CONFIG2 >>> and QPHY_V5_PCS_EQ_CONFIG3. >>> >>> This causes high latency when ASPM is enabled, so fix it! >> >> I have checked against vendor's tree [1]. The registers in question have >> offsets 0x01c0f3e0 / 0x01c0f3e4. The sm8450.dtsi uses 0x1c0f200 as the PCS >> region base for the PCIe PHY1. Thus the correct offsets for the table are >> 0x1e0/0x1e4. >> >> There might be a mistake in the name of the register, but the address >> corresponds to the address in the vendor's tree. >> > > Right. Only the register name is wrong and I've got the offset wrong here. > But the actual latency issue is fixed by clearing the > QPHY_V4_PCS_PCIE_PRESET_P10_POST register in pcs_misc register space. Please, don't use v4 register names in v5.2 tables. If the register matches, could you please add corresponding define? > > I will check with Qcom on this behaviour and post v2 with register name fix. > > Thanks, > Mani > >> [1] https://github.com/MiCode/kernel_devicetree/blob/zeus-s-oss/qcom/waipio-pcie.dtsi#L520 >> >>> >>> Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support") >>> Signed-off-by: Manivannan Sadhasivam >>> --- >>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 ++-- >>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 4 ++-- >>> 2 files changed, 4 insertions(+), 4 deletions(-) >>> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> index 4648467d5cac..b508903d77d0 100644 >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> @@ -1332,8 +1332,8 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { >>> }; >>> static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { >>> - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), >>> - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), >>> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG4, 0x16), >>> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x22), >>> QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), >>> QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), >>> }; >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h >>> index 61a44519f969..cca6455ec98c 100644 >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h >>> @@ -11,7 +11,7 @@ >>> #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 >>> #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 >>> #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 >>> -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 >>> -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 >>> +#define QPHY_V5_PCS_EQ_CONFIG4 0x2e0 >>> +#define QPHY_V5_PCS_EQ_CONFIG5 0x2e4 >>> #endif -- With best wishes Dmitry From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D20B1FA373E for ; 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Wed, 26 Oct 2022 09:45:06 -0700 (PDT) Message-ID: Date: Wed, 26 Oct 2022 19:45:05 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.3 Subject: Re: [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers Content-Language: en-GB To: Manivannan Sadhasivam Cc: vkoul@kernel.org, andersson@kernel.org, kishon@ti.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org References: <20220910063857.17372-1-manivannan.sadhasivam@linaro.org> <20221026143152.GA93939@thinkpad> From: Dmitry Baryshkov In-Reply-To: <20221026143152.GA93939@thinkpad> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221026_094509_857802_0BAEECC8 X-CRM114-Status: GOOD ( 19.67 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 26/10/2022 17:31, Manivannan Sadhasivam wrote: > On Wed, Sep 21, 2022 at 04:06:10PM +0300, Dmitry Baryshkov wrote: >> On 10/09/2022 09:38, Manivannan Sadhasivam wrote: >>> In the PCS region, registers QPHY_V5_PCS_EQ_CONFIG4 and >>> QPHY_V5_PCS_EQ_CONFIG5 should be used instead of QPHY_V5_PCS_EQ_CONFIG2 >>> and QPHY_V5_PCS_EQ_CONFIG3. >>> >>> This causes high latency when ASPM is enabled, so fix it! >> >> I have checked against vendor's tree [1]. The registers in question have >> offsets 0x01c0f3e0 / 0x01c0f3e4. The sm8450.dtsi uses 0x1c0f200 as the PCS >> region base for the PCIe PHY1. Thus the correct offsets for the table are >> 0x1e0/0x1e4. >> >> There might be a mistake in the name of the register, but the address >> corresponds to the address in the vendor's tree. >> > > Right. Only the register name is wrong and I've got the offset wrong here. > But the actual latency issue is fixed by clearing the > QPHY_V4_PCS_PCIE_PRESET_P10_POST register in pcs_misc register space. Please, don't use v4 register names in v5.2 tables. If the register matches, could you please add corresponding define? > > I will check with Qcom on this behaviour and post v2 with register name fix. > > Thanks, > Mani > >> [1] https://github.com/MiCode/kernel_devicetree/blob/zeus-s-oss/qcom/waipio-pcie.dtsi#L520 >> >>> >>> Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support") >>> Signed-off-by: Manivannan Sadhasivam >>> --- >>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 ++-- >>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 4 ++-- >>> 2 files changed, 4 insertions(+), 4 deletions(-) >>> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> index 4648467d5cac..b508903d77d0 100644 >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> @@ -1332,8 +1332,8 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { >>> }; >>> static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { >>> - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), >>> - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), >>> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG4, 0x16), >>> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x22), >>> QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), >>> QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), >>> }; >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h >>> index 61a44519f969..cca6455ec98c 100644 >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h >>> @@ -11,7 +11,7 @@ >>> #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 >>> #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 >>> #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 >>> -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 >>> -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 >>> +#define QPHY_V5_PCS_EQ_CONFIG4 0x2e0 >>> +#define QPHY_V5_PCS_EQ_CONFIG5 0x2e4 >>> #endif -- With best wishes Dmitry -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy