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diff for duplicates of <bdec8a59-89c0-4047-8365-5b2fa23732bb@rivosinc.com>

diff --git a/a/1.txt b/N1/1.txt
index 781544e..f687d0a 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,16 +1,16 @@
 
 
 On 25/11/2024 15:26, Andrew Jones wrote:
-> On Mon, Nov 25, 2024 at 03:13:01PM +0100, Cl?ment L?ger wrote:
+> On Mon, Nov 25, 2024 at 03:13:01PM +0100, Clément Léger wrote:
 >>
 >>
 >> On 25/11/2024 14:50, Andrew Jones wrote:
->>> On Mon, Nov 25, 2024 at 12:54:47PM +0100, Cl?ment L?ger wrote:
+>>> On Mon, Nov 25, 2024 at 12:54:47PM +0100, Clément Léger wrote:
 >>>> Add a SSE entry assembly code to handle SSE events. Events should be
 >>>> registered with a struct sse_handler_arg containing a correct stack and
 >>>> handler function.
 >>>>
->>>> Signed-off-by: Cl?ment L?ger <cleger@rivosinc.com>
+>>>> Signed-off-by: Clément Léger <cleger@rivosinc.com>
 >>>> ---
 >>>>  riscv/Makefile          |   1 +
 >>>>  lib/riscv/asm/sse.h     |  16 +++++++
@@ -73,7 +73,7 @@ On 25/11/2024 15:26, Andrew Jones wrote:
 >>>> +/*
 >>>> + * SBI SSE entry code
 >>>> + *
->>>> + * Copyright (C) 2024, Rivos Inc., Cl?ment L?ger <cleger@rivosinc.com>
+>>>> + * Copyright (C) 2024, Rivos Inc., Clément Léger <cleger@rivosinc.com>
 >>>> + */
 >>>> +#include <asm/asm.h>
 >>>> +#include <asm/asm-offsets.h>
@@ -268,7 +268,7 @@ On 25/11/2024 15:26, Andrew Jones wrote:
 >>> -/*
 >>> - * SBI SSE entry code
 >>> - *
->>> - * Copyright (C) 2024, Rivos Inc., Cl?ment L?ger <cleger@rivosinc.com>
+>>> - * Copyright (C) 2024, Rivos Inc., Clément Léger <cleger@rivosinc.com>
 >>> - */
 >>> -#include <asm/asm.h>
 >>> -#include <asm/asm-offsets.h>
diff --git a/a/content_digest b/N1/content_digest
index 186b1fc..fdb59bb 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -4,24 +4,29 @@
  "ref\05853b922-da5a-409e-875b-084da78999bd@rivosinc.com\0"
  "ref\020241125-23cfeccc06900429ecd2a31d@orel\0"
  "From\0Cl\303\251ment L\303\251ger <cleger@rivosinc.com>\0"
- "Subject\0[kvm-unit-tests PATCH v3 3/4] riscv: lib: Add SSE assembly entry handling\0"
+ "Subject\0Re: [kvm-unit-tests PATCH v3 3/4] riscv: lib: Add SSE assembly entry handling\0"
  "Date\0Mon, 25 Nov 2024 15:41:23 +0100\0"
- "To\0kvm-riscv@lists.infradead.org\0"
+ "To\0Andrew Jones <andrew.jones@linux.dev>\0"
+ "Cc\0kvm@vger.kernel.org"
+  kvm-riscv@lists.infradead.org
+  Andrew Jones <ajones@ventanamicro.com>
+  Anup Patel <apatel@ventanamicro.com>
+ " Atish Patra <atishp@rivosinc.com>\0"
  "\00:1\0"
  "b\0"
  "\n"
  "\n"
  "On 25/11/2024 15:26, Andrew Jones wrote:\n"
- "> On Mon, Nov 25, 2024 at 03:13:01PM +0100, Cl?ment L?ger wrote:\n"
+ "> On Mon, Nov 25, 2024 at 03:13:01PM +0100, Cl\303\251ment L\303\251ger wrote:\n"
  ">>\n"
  ">>\n"
  ">> On 25/11/2024 14:50, Andrew Jones wrote:\n"
- ">>> On Mon, Nov 25, 2024 at 12:54:47PM +0100, Cl?ment L?ger wrote:\n"
+ ">>> On Mon, Nov 25, 2024 at 12:54:47PM +0100, Cl\303\251ment L\303\251ger wrote:\n"
  ">>>> Add a SSE entry assembly code to handle SSE events. Events should be\n"
  ">>>> registered with a struct sse_handler_arg containing a correct stack and\n"
  ">>>> handler function.\n"
  ">>>>\n"
- ">>>> Signed-off-by: Cl?ment L?ger <cleger@rivosinc.com>\n"
+ ">>>> Signed-off-by: Cl\303\251ment L\303\251ger <cleger@rivosinc.com>\n"
  ">>>> ---\n"
  ">>>>  riscv/Makefile          |   1 +\n"
  ">>>>  lib/riscv/asm/sse.h     |  16 +++++++\n"
@@ -84,7 +89,7 @@
  ">>>> +/*\n"
  ">>>> + * SBI SSE entry code\n"
  ">>>> + *\n"
- ">>>> + * Copyright (C) 2024, Rivos Inc., Cl?ment L?ger <cleger@rivosinc.com>\n"
+ ">>>> + * Copyright (C) 2024, Rivos Inc., Cl\303\251ment L\303\251ger <cleger@rivosinc.com>\n"
  ">>>> + */\n"
  ">>>> +#include <asm/asm.h>\n"
  ">>>> +#include <asm/asm-offsets.h>\n"
@@ -279,7 +284,7 @@
  ">>> -/*\n"
  ">>> - * SBI SSE entry code\n"
  ">>> - *\n"
- ">>> - * Copyright (C) 2024, Rivos Inc., Cl?ment L?ger <cleger@rivosinc.com>\n"
+ ">>> - * Copyright (C) 2024, Rivos Inc., Cl\303\251ment L\303\251ger <cleger@rivosinc.com>\n"
  ">>> - */\n"
  ">>> -#include <asm/asm.h>\n"
  ">>> -#include <asm/asm-offsets.h>\n"
@@ -581,4 +586,4 @@
  "> Thanks,\n"
  > drew
 
-f6cddff6f016dfcaea29a5eabae34c6179c773df89cf23441ad81f77a61a65cb
+141fe9de344240909a211669371499187b7a2c300807d20a87f83bb1daa85743

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