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Mon, 14 Jul 2025 13:27:40 +0000 Message-ID: Date: Mon, 14 Jul 2025 15:27:32 +0200 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 01/33] drm/amdgpu: clean up sdma reset functions To: Alex Deucher , amd-gfx@lists.freedesktop.org, sasundar@amd.com References: <20250711224024.410506-1-alexander.deucher@amd.com> <20250711224024.410506-2-alexander.deucher@amd.com> Content-Language: en-US From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: <20250711224024.410506-2-alexander.deucher@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: FR2P281CA0011.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a::21) To PH7PR12MB5685.namprd12.prod.outlook.com (2603:10b6:510:13c::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH7PR12MB5685:EE_|MN2PR12MB4237:EE_ X-MS-Office365-Filtering-Correlation-Id: 716f1c2e-40d6-4d8e-0e6d-08ddc2da34c9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|1800799024; 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> break; > default: > @@ -1544,11 +1545,18 @@ static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring, > struct amdgpu_fence *timedout_fence) > { > struct amdgpu_device *adev = ring->adev; > - u32 inst_id = ring->me; > int r; > > + if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) > + return -EOPNOTSUPP; > + > + if (ring->me >= adev->sdma.num_instances) { > + dev_err(adev->dev, "sdma instance not found\n"); > + return -EINVAL; > + } > + > amdgpu_amdkfd_suspend(adev, true); > - r = amdgpu_sdma_reset_engine(adev, inst_id, false); > + r = amdgpu_sdma_reset_engine(adev, ring->me, false); > amdgpu_amdkfd_resume(adev, true); > > return r; > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > index 6843c2c3d71f5..e542195972dd4 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > @@ -1347,11 +1347,13 @@ static int sdma_v5_2_sw_init(struct amdgpu_ip_block *ip_block) > case IP_VERSION(5, 2, 2): > case IP_VERSION(5, 2, 3): > case IP_VERSION(5, 2, 4): > - if (adev->sdma.instance[0].fw_version >= 76) > + if ((adev->sdma.instance[0].fw_version >= 76) && > + !amdgpu_sriov_vf(adev)) > adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; > break; > case IP_VERSION(5, 2, 5): > - if (adev->sdma.instance[0].fw_version >= 34) > + if ((adev->sdma.instance[0].fw_version >= 34) && > + !amdgpu_sriov_vf(adev)) > adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; > break; > default: > @@ -1457,11 +1459,18 @@ static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring, > struct amdgpu_fence *timedout_fence) > { > struct amdgpu_device *adev = ring->adev; > - u32 inst_id = ring->me; > int r; > > + if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) > + return -EOPNOTSUPP; > + > + if (ring->me >= adev->sdma.num_instances) { > + dev_err(adev->dev, "sdma instance not found\n"); > + return -EINVAL; > + } > + > amdgpu_amdkfd_suspend(adev, true); > - r = amdgpu_sdma_reset_engine(adev, inst_id, false); > + r = amdgpu_sdma_reset_engine(adev, ring->me, false); > amdgpu_amdkfd_resume(adev, true); > > return r; > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c > index d2effa5318176..c08e9a6cf6827 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c > @@ -1355,7 +1355,8 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) > case IP_VERSION(6, 0, 0): > case IP_VERSION(6, 0, 2): > case IP_VERSION(6, 0, 3): > - if (adev->sdma.instance[0].fw_version >= 21) > + if ((adev->sdma.instance[0].fw_version >= 21) && > + !amdgpu_sriov_vf(adev)) > adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; > break; > default: > @@ -1575,18 +1576,13 @@ static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, > struct amdgpu_fence *timedout_fence) > { > struct amdgpu_device *adev = ring->adev; > - int i, r; > - > - if (amdgpu_sriov_vf(adev)) > - return -EINVAL; > + int r; > > - for (i = 0; i < adev->sdma.num_instances; i++) { > - if (ring == &adev->sdma.instance[i].ring) > - break; > - } > + if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) > + return -EOPNOTSUPP; > > - if (i == adev->sdma.num_instances) { > - DRM_ERROR("sdma instance not found\n"); > + if (ring->me >= adev->sdma.num_instances) { > + dev_err(adev->dev, "sdma instance not found\n"); > return -EINVAL; > } > > @@ -1596,7 +1592,7 @@ static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, > if (r) > return r; > > - r = sdma_v6_0_gfx_resume_instance(adev, i, true); > + r = sdma_v6_0_gfx_resume_instance(adev, ring->me, true); > if (r) > return r; > amdgpu_fence_driver_force_completion(ring); > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c > index 99a080bad2a3d..ba1f3e3b6eb61 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c > @@ -807,18 +807,13 @@ static int sdma_v7_0_reset_queue(struct amdgpu_ring *ring, > struct amdgpu_fence *timedout_fence) > { > struct amdgpu_device *adev = ring->adev; > - int i, r; > - > - if (amdgpu_sriov_vf(adev)) > - return -EINVAL; > + int r; > > - for (i = 0; i < adev->sdma.num_instances; i++) { > - if (ring == &adev->sdma.instance[i].ring) > - break; > - } > + if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) > + return -EOPNOTSUPP; > > - if (i == adev->sdma.num_instances) { > - DRM_ERROR("sdma instance not found\n"); > + if (ring->me >= adev->sdma.num_instances) { > + dev_err(adev->dev, "sdma instance not found\n"); > return -EINVAL; > } > > @@ -828,7 +823,7 @@ static int sdma_v7_0_reset_queue(struct amdgpu_ring *ring, > if (r) > return r; > > - r = sdma_v7_0_gfx_resume_instance(adev, i, true); > + r = sdma_v7_0_gfx_resume_instance(adev, ring->me, true); > if (r) > return r; > amdgpu_fence_driver_force_completion(ring); > @@ -1346,7 +1341,8 @@ static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block) > > adev->sdma.supported_reset = > amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); > - adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; > + if (!amdgpu_sriov_vf(adev)) > + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; > > r = amdgpu_sdma_sysfs_reset_mask_init(adev); > if (r)