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Thu, 16 Jul 2026 21:01:58 -0700 (PDT) X-Received: by 2002:a05:6a21:a87:b0:3c3:a8a4:e71a with SMTP id adf61e73a8af0-3c3ad6035d4mr882263637.11.1784260918344; Thu, 16 Jul 2026 21:01:58 -0700 (PDT) Received: from [10.217.219.121] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3142a1bb770sm1822442eec.16.2026.07.16.21.01.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Jul 2026 21:01:57 -0700 (PDT) Message-ID: Date: Fri, 17 Jul 2026 09:31:51 +0530 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/2] dt-bindings: qcom,snps-dwc3: Add property indicating presence of eUSB2 phy To: Peter Chen , Thinh Nguyen , Konrad Dybcio Cc: Krzysztof Kozlowski , Dmitry Baryshkov , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , "linux-arm-msm@vger.kernel.org" , "linux-usb@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" References: Content-Language: en-US From: Krishna Kurapati In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: S1L6-SOuHZsgiYHsNYe_VZRReh2RbuPm X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE3MDAzNSBTYWx0ZWRfX37xEQQg1Jkqj 7XR/MLUiwvH48RUvUWzaFIJTVfy4WJFwS840DUl0qjqobFgCvTKxOP/tVbpMhBWRi2ILOw1Okix ioZBeOpPjHE1ZXzC+2riaNuKmV/vNLI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE3MDAzNSBTYWx0ZWRfX/3uQg93PmVFl RNzIRAIJ+tWKGJSQXL2cW6x5DD6c9wooSF1z9yeXEP0jRhT0hiU8ZOImo475ir52z6Fntq4hmqY OvBXbFrJd139kUVhXZDRSyfsReYPoiKT8azHmSSH7kG/HcuatqBKVuk7oGALHJ4jCWRTlZ+djBG BOKzDCa4NJxDX1rCF65an4Yzd4pL6Rnfhzj/AuV9+YGA9PdqaBvnFYC2aDRpjkG/Lly6mr1185I OePZkMbb6O7sPQIzY28ZXYpEfoF7dWCxmTmPKJbL/y4yUTFVCqjgg80Y29exNjY0E8k2hU3NwqX 3LQM8NYvytirOsYB1mzXALhwfnuXCR7Bq4VuRzYmDdx5m8v0gTTHaFZmMDyir1pA52uqVlBaNuu mYI0i8EAeIcy2iWInYUMV/XnXTFSm6PrUj2bShyx07pZxqxfgRs8YZKkgaYajR8v3mN2M5gxsNd VY+YU0a6SPvkdxuysBA== X-Authority-Analysis: v=2.4 cv=NcTWEWD4 c=1 sm=1 tr=0 ts=6a59a937 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=081tR47BLqD6ycLrW70A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: S1L6-SOuHZsgiYHsNYe_VZRReh2RbuPm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-17_01,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 phishscore=0 bulkscore=0 spamscore=0 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607170035 On 7/17/2026 9:12 AM, Peter Chen wrote: > On 26-07-17 01:56:59, Thinh Nguyen wrote: >> On Thu, Jul 16, 2026, Peter Chen wrote: >>> On 26-07-17 00:06:37, Thinh Nguyen wrote: >>>>> >>>>> I have seen fewer platforms use "phy_type" at dts for arm64, dwc3 >>>>> core uses it only for special cases and the code was added for >>>>> ten years ago. For the default situation, we may not need to >>>>> change DWC3_GUSB2PHYCFG_EUSB2OPMODE value for UTMI+, Thinh, is it >>>>> correct? >>>>> >>>> >>>> The GUSB2PHYCFG.eUSB2OPMODE is only relevant for host mode and mainly >>>> for electrical compliance. Usually by default, the CoreConsultant >>>> setting should have this set correctly. So not explicitly setting it >>>> should be functionally fine (IIRC). >>>> >>>> That said, this is separate from the GUSB2PHYCFG.PHYIF, which the core >>>> uses dwc->hsphy_mode to indicate whether the UTMI interface is 8-bit or >>>> 16-bit. >>>> >>> >>> Why only rockchip uses this "phy_type" property, why other SoC vendors >>> no this requirement for UTMI width setting? >>> >> >> Not just rockchip, some tegra and hikey also use it. Some old qcom dts >> files also have it for ulpi. > > Tegra and old qcom platforms use chipidea, hikey uses dwc3. > >> >> It is typically set when the coreConsultant default differs from what >> the platform needs, so the driver can override it with the correct >> setting. >> >> My point is that changing "phy_type" definition is more involved than it >> looks. I'm open to alternatives. >> > > I know your concern that in case the eUSB2 PHY SoC wants to change UTMI > width, it can't do that. Are there controller register know it connects > eUSB2 PHY? > > For the place to put "eusb2" for phy type, I still think enum > usb_phy_interface at: include/linux/usb/phy.h is the most suitable > place, would you have any alternatives? > > Another solution is using generic PHY API phy_get_mode, set fixed "eusb2" > mode at eUSB2 PHY driver, but it depends on PHY driver doesn't have > different settings for device and host mode. > Konrad did suggest this on v3: https://lore.kernel.org/all/3de365a0-4632-42ea-8a8a-5a4765945a76@oss.qualcomm.com/ This involves cleaning all drivers using these enums if we take that route. Regards, Krishna, > Other solution is compare the generic PHY compatible string at dwc3 qcom > glue layer, it depends on eUSB2 PHY compatible string always contains > "eusb2-phy" > > I prefer the solution that extend enum usb_phy_interface for eUSB2 PHY, > it uses existed kernel structure and device tree binding. >