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L3N5c3JlZy5owqDCoMKgwqDCoMKgwqDCoMKgwqDCoCB8wqAgMyArLQo+Pj4gwqBhcmNoL2FybTY0 L2tlcm5lbC9hc20tb2Zmc2V0cy5jwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCB8wqAgMyArCj4+PiDC oGFyY2gvYXJtNjQva3ZtL2h5cC9lbnRyeS5TwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqAgfMKgIDcgKysKPj4+IMKgYXJjaC9hcm02NC9rdm0vaHlwL2luY2x1ZGUvaHlwL3N5c3JlZy1z ci5oIHzCoCA0ICsrCj4+PiDCoGFyY2gvYXJtNjQva3ZtL3N5c19yZWdzLmPCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgIHwgMTQgKystLQo+Pj4gwqA3IGZpbGVzIGNoYW5nZWQsIDEw NCBpbnNlcnRpb25zKCspLCA1IGRlbGV0aW9ucygtKQo+Pj4gwqBjcmVhdGUgbW9kZSAxMDA2NDQg YXJjaC9hcm02NC9pbmNsdWRlL2FzbS9rdm1fbXRlLmgKPj4+IAo+Pj4gZGlmZiAtLWdpdCBhL2Fy Y2gvYXJtNjQvaW5jbHVkZS9hc20va3ZtX2hvc3QuaAo+Pj4gYi9hcmNoL2FybTY0L2luY2x1ZGUv YXNtL2t2bV9ob3N0LmgKPj4+IGluZGV4IDExYmVkYTg1ZWU3ZS4uNTE1OTBhMzk3ZTRiIDEwMDY0 NAo+Pj4gLS0tIGEvYXJjaC9hcm02NC9pbmNsdWRlL2FzbS9rdm1faG9zdC5oCj4+PiArKysgYi9h cmNoL2FybTY0L2luY2x1ZGUvYXNtL2t2bV9ob3N0LmgKPj4+IEBAIC0xNDgsNiArMTQ4LDggQEAg ZW51bSB2Y3B1X3N5c3JlZyB7Cj4+PiDCoMKgwqDCoCBTQ1RMUl9FTDEswqDCoMKgIC8qIFN5c3Rl bSBDb250cm9sIFJlZ2lzdGVyICovCj4+PiDCoMKgwqDCoCBBQ1RMUl9FTDEswqDCoMKgIC8qIEF1 eGlsaWFyeSBDb250cm9sIFJlZ2lzdGVyICovCj4+PiDCoMKgwqDCoCBDUEFDUl9FTDEswqDCoMKg IC8qIENvcHJvY2Vzc29yIEFjY2VzcyBDb250cm9sICovCj4+PiArwqDCoMKgIFJHU1JfRUwxLMKg wqDCoCAvKiBSYW5kb20gQWxsb2NhdGlvbiBUYWcgU2VlZCBSZWdpc3RlciAqLwo+Pj4gK8KgwqDC oCBHQ1JfRUwxLMKgwqDCoCAvKiBUYWcgQ29udHJvbCBSZWdpc3RlciAqLwo+Pj4gwqDCoMKgwqAg WkNSX0VMMSzCoMKgwqAgLyogU1ZFIENvbnRyb2wgKi8KPj4+IMKgwqDCoMKgIFRUQlIwX0VMMSzC oMKgwqAgLyogVHJhbnNsYXRpb24gVGFibGUgQmFzZSBSZWdpc3RlciAwICovCj4+PiDCoMKgwqDC oCBUVEJSMV9FTDEswqDCoMKgIC8qIFRyYW5zbGF0aW9uIFRhYmxlIEJhc2UgUmVnaXN0ZXIgMSAq Lwo+Pj4gQEAgLTE2NCw2ICsxNjYsOCBAQCBlbnVtIHZjcHVfc3lzcmVnIHsKPj4+IMKgwqDCoMKg IFRQSURSX0VMMSzCoMKgwqAgLyogVGhyZWFkIElELCBQcml2aWxlZ2VkICovCj4+PiDCoMKgwqDC oCBBTUFJUl9FTDEswqDCoMKgIC8qIEF1eCBNZW1vcnkgQXR0cmlidXRlIEluZGlyZWN0aW9uIFJl Z2lzdGVyICovCj4+PiDCoMKgwqDCoCBDTlRLQ1RMX0VMMSzCoMKgwqAgLyogVGltZXIgQ29udHJv bCBSZWdpc3RlciAoRUwxKSAqLwo+Pj4gK8KgwqDCoCBURlNSRTBfRUwxLMKgwqDCoCAvKiBUYWcg RmF1bHQgU3RhdHVzIFJlZ2lzdGVyIChFTDApICovCj4+PiArwqDCoMKgIFRGU1JfRUwxLMKgwqDC oCAvKiBUYWcgRmF1bHQgU3RhdXRzIFJlZ2lzdGVyIChFTDEpICovCj4+IAo+PiBzL1N0YXV0cy9T dGF0dXMvCj4+IAo+PiBJcyB0aGVyZSBhbnkgcmVhc29uIHdoeSB0aGUgTVRFIHJlZ2lzdGVycyBh cmVuJ3QgZ3JvdXBlZCB0b2dldGhlcj8KPiAKPiBJIGhhcyBiZWVuIHVuZGVyIHRoZSBpbXByZXNz aW9uIHRoaXMgbGlzdCBpcyBzb3J0ZWQgYnkgdGhlIGVuY29kaW5nIG9mCj4gdGhlIHN5c3RlbSBy ZWdpc3RlcnMsIGFsdGhvdWdoIGRvdWJsZSBjaGVja2luZyBJJ3ZlIHNjcmV3ZWQgdXAgdGhlCj4g b3JkZXIgb2YgVEZTUkUwX0VMMS9URlNSX0VMMSwgYW5kIG5vdCBhbGwgdGhlIG90aGVyIGZpZWxk cyBhcmUgc29ydGVkCj4gdGhhdCB3YXkuCgpJdCBncmV3IG9yZ2FuaWNhbGx5LCBhbmQgd2FzIGlu aXRpYWxseSBtYXRjaGluZyB0aGUgb3JpZ2luYWwgb3JkZXIKb2YgdGhlIHNhdmUvcmVzdG9yZSBz ZXF1ZW5jZS4gVGhpcyBvcmRlciBoYXMgbG9uZyBkaXNhcHBlYXJlZCB3aXRoClZIRSwgYW5kIHRo aXMgaXMgZXNzZW50aWFsbHkgbm90aGluZyBtb3JlIHRoYW4gYSBiYWcgb2YgaW5kaWNlcwooYWx0 aG91Z2ggTlYgZG9lcyBicmluZyBzb21lIG9yZGVyIGJhY2sgdG8gZGVhbCB3aXRoIFZOQ1ItYmFj a2VkCnJlZ2lzdGVycykuCgpbLi4uXQoKPj4+IGRpZmYgLS1naXQgYS9hcmNoL2FybTY0L2t2bS9o eXAvaW5jbHVkZS9oeXAvc3lzcmVnLXNyLmgKPj4+IGIvYXJjaC9hcm02NC9rdm0vaHlwL2luY2x1 ZGUvaHlwL3N5c3JlZy1zci5oCj4+PiBpbmRleCBjY2U0M2JmZTE1OGYuLjk0ZDk3MzZmMDEzMyAx MDA2NDQKPj4+IC0tLSBhL2FyY2gvYXJtNjQva3ZtL2h5cC9pbmNsdWRlL2h5cC9zeXNyZWctc3Iu aAo+Pj4gKysrIGIvYXJjaC9hcm02NC9rdm0vaHlwL2luY2x1ZGUvaHlwL3N5c3JlZy1zci5oCj4+ PiBAQCAtNDUsNiArNDUsOCBAQCBzdGF0aWMgaW5saW5lIHZvaWQgX19zeXNyZWdfc2F2ZV9lbDFf c3RhdGUoc3RydWN0Cj4+PiBrdm1fY3B1X2NvbnRleHQgKmN0eHQpCj4+PiDCoMKgwqDCoCBjdHh0 X3N5c19yZWcoY3R4dCwgQ05US0NUTF9FTDEpwqDCoMKgID0gCj4+PiByZWFkX3N5c3JlZ19lbDEo U1lTX0NOVEtDVEwpOwo+Pj4gwqDCoMKgwqAgY3R4dF9zeXNfcmVnKGN0eHQsIFBBUl9FTDEpwqDC oMKgID0gcmVhZF9zeXNyZWdfcGFyKCk7Cj4+PiDCoMKgwqDCoCBjdHh0X3N5c19yZWcoY3R4dCwg VFBJRFJfRUwxKcKgwqDCoCA9IHJlYWRfc3lzcmVnKHRwaWRyX2VsMSk7Cj4+PiArwqDCoMKgIGlm IChzeXN0ZW1fc3VwcG9ydHNfbXRlKCkpCj4+PiArwqDCoMKgwqDCoMKgwqAgY3R4dF9zeXNfcmVn KGN0eHQsIFRGU1JfRUwxKSA9IHJlYWRfc3lzcmVnX2VsMShTWVNfVEZTUik7Cj4+IAo+PiBJIGFs cmVhZHkgYXNrZWQgZm9yIGl0LCBhbmQgSSdtIGdvaW5nIHRvIGFzayBmb3IgaXQgYWdhaW46Cj4+ IE1vc3Qgb2YgdGhlIHN5c3JlZyBzYXZlL3Jlc3RvcmUgaXMgZ3VhcmRlZCBieSBhIHBlci12Y3B1 IGNoZWNrCj4+IChIQ1JfRUwyLkFUQSksIHdoaWxlIHRoaXMgb25lIGlzIHVuY29uZGl0aW9uYWxs eSBzYXZlZC9yZXN0b3JlCj4+IGlmIHRoZSBob3N0IGlzIE1URSBjYXBhYmxlLiBXaHkgaXMgdGhh dCBzbz8KPiAKPiBTb3JyeSwgSSB0aG91Z2h0IHlvdXIgY29uY2VybiB3YXMgZm9yIHJlZ2lzdGVy cyB0aGF0IGFmZmVjdCB0aGUgaG9zdAo+IChhcyB0aGV5IGFyZSBvYnZpb3VzbHkgbW9yZSBwZXJm b3JtYW5jZSBjcml0aWNhbCBhcyB0aGV5IGFyZSBoaXQgb24KPiBldmVyeSBndWVzdCBleGl0KS4g QWx0aG91Z2ggSSBndWVzcyB0aGF0J3MgaW5jb3JyZWN0IGZvciBuVkhFIHdoaWNoIGlzCj4gd2hh dCBhbGwgdGhlIGNvb2wga2lkcyB3YW50IG5vdyA7KQoKSSB0aGluayB3ZSB3YW50IGJvdGggY29y cmVjdG5lc3MgKmFuZCogcGVyZm9ybWFuY2UsIGZvciBib3RoIFZIRQphbmQgblZIRS4gVGhpbmdz IGxpa2UgRUwwIHJlZ2lzdGVycyBzaG91bGQgYmUgYWJsZSB0byBiZSBtb3ZlZAp0byBsb2FkL3B1 dCBvbiBhbGwgaW1wbGVtZW50YXRpb25zLCBhbmQgdGhlIGNvcnJlY3Qgc3dpdGNoaW5nCmJlIGRv bmUgYXQgdGhlIHJpZ2h0IHNwb3Qgb25seSB3aGVuIHJlcXVpcmVkLgoKVGhhbmtzLAoKICAgICAg ICAgTS4KLS0gCkphenogaXMgbm90IGRlYWQuIEl0IGp1c3Qgc21lbGxzIGZ1bm55Li4uCl9fX19f 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disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1l7g3J-00C1uA-9o; Thu, 04 Feb 2021 14:56:13 +0000 MIME-Version: 1.0 Date: Thu, 04 Feb 2021 14:56:13 +0000 From: Marc Zyngier To: Steven Price Subject: Re: [PATCH v7 1/3] arm64: kvm: Save/restore MTE registers In-Reply-To: References: <20210115152811.8398-1-steven.price@arm.com> <20210115152811.8398-2-steven.price@arm.com> User-Agent: Roundcube Webmail/1.4.10 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: steven.price@arm.com, catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave.Martin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, qemu-devel@nongnu.org, quintela@redhat.com, dgilbert@redhat.com, richard.henderson@linaro.org, peter.maydell@linaro.org, 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linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gMjAyMS0wMi0wNCAxNDozMywgU3RldmVuIFByaWNlIHdyb3RlOgo+IE9uIDAyLzAyLzIwMjEg MTU6MzYsIE1hcmMgWnluZ2llciB3cm90ZToKPj4gT24gMjAyMS0wMS0xNSAxNToyOCwgU3RldmVu IFByaWNlIHdyb3RlOgo+Pj4gRGVmaW5lIHRoZSBuZXcgc3lzdGVtIHJlZ2lzdGVycyB0aGF0IE1U RSBpbnRyb2R1Y2VzIGFuZCBjb250ZXh0IAo+Pj4gc3dpdGNoCj4+PiB0aGVtLiBUaGUgTVRFIGZl YXR1cmUgaXMgc3RpbGwgaGlkZGVuIGZyb20gdGhlIElEIHJlZ2lzdGVyIGFzIGl0IAo+Pj4gaXNu J3QKPj4+IHN1cHBvcnRlZCBpbiBhIFZNIHlldC4KPj4+IAo+Pj4gU2lnbmVkLW9mZi1ieTogU3Rl dmVuIFByaWNlIDxzdGV2ZW4ucHJpY2VAYXJtLmNvbT4KPj4+IC0tLQo+Pj4gwqBhcmNoL2FybTY0 L2luY2x1ZGUvYXNtL2t2bV9ob3N0LmjCoMKgwqDCoMKgwqDCoMKgwqAgfMKgIDQgKysKPj4+IMKg YXJjaC9hcm02NC9pbmNsdWRlL2FzbS9rdm1fbXRlLmjCoMKgwqDCoMKgwqDCoMKgwqDCoCB8IDc0 IAo+Pj4gKysrKysrKysrKysrKysrKysrKysrKwo+Pj4gwqBhcmNoL2FybTY0L2luY2x1ZGUvYXNt L3N5c3JlZy5owqDCoMKgwqDCoMKgwqDCoMKgwqDCoCB8wqAgMyArLQo+Pj4gwqBhcmNoL2FybTY0 L2tlcm5lbC9hc20tb2Zmc2V0cy5jwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCB8wqAgMyArCj4+PiDC oGFyY2gvYXJtNjQva3ZtL2h5cC9lbnRyeS5TwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqAgfMKgIDcgKysKPj4+IMKgYXJjaC9hcm02NC9rdm0vaHlwL2luY2x1ZGUvaHlwL3N5c3JlZy1z ci5oIHzCoCA0ICsrCj4+PiDCoGFyY2gvYXJtNjQva3ZtL3N5c19yZWdzLmPCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgIHwgMTQgKystLQo+Pj4gwqA3IGZpbGVzIGNoYW5nZWQsIDEw NCBpbnNlcnRpb25zKCspLCA1IGRlbGV0aW9ucygtKQo+Pj4gwqBjcmVhdGUgbW9kZSAxMDA2NDQg YXJjaC9hcm02NC9pbmNsdWRlL2FzbS9rdm1fbXRlLmgKPj4+IAo+Pj4gZGlmZiAtLWdpdCBhL2Fy Y2gvYXJtNjQvaW5jbHVkZS9hc20va3ZtX2hvc3QuaAo+Pj4gYi9hcmNoL2FybTY0L2luY2x1ZGUv YXNtL2t2bV9ob3N0LmgKPj4+IGluZGV4IDExYmVkYTg1ZWU3ZS4uNTE1OTBhMzk3ZTRiIDEwMDY0 NAo+Pj4gLS0tIGEvYXJjaC9hcm02NC9pbmNsdWRlL2FzbS9rdm1faG9zdC5oCj4+PiArKysgYi9h cmNoL2FybTY0L2luY2x1ZGUvYXNtL2t2bV9ob3N0LmgKPj4+IEBAIC0xNDgsNiArMTQ4LDggQEAg ZW51bSB2Y3B1X3N5c3JlZyB7Cj4+PiDCoMKgwqDCoCBTQ1RMUl9FTDEswqDCoMKgIC8qIFN5c3Rl bSBDb250cm9sIFJlZ2lzdGVyICovCj4+PiDCoMKgwqDCoCBBQ1RMUl9FTDEswqDCoMKgIC8qIEF1 eGlsaWFyeSBDb250cm9sIFJlZ2lzdGVyICovCj4+PiDCoMKgwqDCoCBDUEFDUl9FTDEswqDCoMKg IC8qIENvcHJvY2Vzc29yIEFjY2VzcyBDb250cm9sICovCj4+PiArwqDCoMKgIFJHU1JfRUwxLMKg wqDCoCAvKiBSYW5kb20gQWxsb2NhdGlvbiBUYWcgU2VlZCBSZWdpc3RlciAqLwo+Pj4gK8KgwqDC oCBHQ1JfRUwxLMKgwqDCoCAvKiBUYWcgQ29udHJvbCBSZWdpc3RlciAqLwo+Pj4gwqDCoMKgwqAg WkNSX0VMMSzCoMKgwqAgLyogU1ZFIENvbnRyb2wgKi8KPj4+IMKgwqDCoMKgIFRUQlIwX0VMMSzC oMKgwqAgLyogVHJhbnNsYXRpb24gVGFibGUgQmFzZSBSZWdpc3RlciAwICovCj4+PiDCoMKgwqDC oCBUVEJSMV9FTDEswqDCoMKgIC8qIFRyYW5zbGF0aW9uIFRhYmxlIEJhc2UgUmVnaXN0ZXIgMSAq Lwo+Pj4gQEAgLTE2NCw2ICsxNjYsOCBAQCBlbnVtIHZjcHVfc3lzcmVnIHsKPj4+IMKgwqDCoMKg IFRQSURSX0VMMSzCoMKgwqAgLyogVGhyZWFkIElELCBQcml2aWxlZ2VkICovCj4+PiDCoMKgwqDC oCBBTUFJUl9FTDEswqDCoMKgIC8qIEF1eCBNZW1vcnkgQXR0cmlidXRlIEluZGlyZWN0aW9uIFJl Z2lzdGVyICovCj4+PiDCoMKgwqDCoCBDTlRLQ1RMX0VMMSzCoMKgwqAgLyogVGltZXIgQ29udHJv bCBSZWdpc3RlciAoRUwxKSAqLwo+Pj4gK8KgwqDCoCBURlNSRTBfRUwxLMKgwqDCoCAvKiBUYWcg RmF1bHQgU3RhdHVzIFJlZ2lzdGVyIChFTDApICovCj4+PiArwqDCoMKgIFRGU1JfRUwxLMKgwqDC oCAvKiBUYWcgRmF1bHQgU3RhdXRzIFJlZ2lzdGVyIChFTDEpICovCj4+IAo+PiBzL1N0YXV0cy9T dGF0dXMvCj4+IAo+PiBJcyB0aGVyZSBhbnkgcmVhc29uIHdoeSB0aGUgTVRFIHJlZ2lzdGVycyBh cmVuJ3QgZ3JvdXBlZCB0b2dldGhlcj8KPiAKPiBJIGhhcyBiZWVuIHVuZGVyIHRoZSBpbXByZXNz aW9uIHRoaXMgbGlzdCBpcyBzb3J0ZWQgYnkgdGhlIGVuY29kaW5nIG9mCj4gdGhlIHN5c3RlbSBy ZWdpc3RlcnMsIGFsdGhvdWdoIGRvdWJsZSBjaGVja2luZyBJJ3ZlIHNjcmV3ZWQgdXAgdGhlCj4g b3JkZXIgb2YgVEZTUkUwX0VMMS9URlNSX0VMMSwgYW5kIG5vdCBhbGwgdGhlIG90aGVyIGZpZWxk cyBhcmUgc29ydGVkCj4gdGhhdCB3YXkuCgpJdCBncmV3IG9yZ2FuaWNhbGx5LCBhbmQgd2FzIGlu aXRpYWxseSBtYXRjaGluZyB0aGUgb3JpZ2luYWwgb3JkZXIKb2YgdGhlIHNhdmUvcmVzdG9yZSBz ZXF1ZW5jZS4gVGhpcyBvcmRlciBoYXMgbG9uZyBkaXNhcHBlYXJlZCB3aXRoClZIRSwgYW5kIHRo aXMgaXMgZXNzZW50aWFsbHkgbm90aGluZyBtb3JlIHRoYW4gYSBiYWcgb2YgaW5kaWNlcwooYWx0 aG91Z2ggTlYgZG9lcyBicmluZyBzb21lIG9yZGVyIGJhY2sgdG8gZGVhbCB3aXRoIFZOQ1ItYmFj a2VkCnJlZ2lzdGVycykuCgpbLi4uXQoKPj4+IGRpZmYgLS1naXQgYS9hcmNoL2FybTY0L2t2bS9o eXAvaW5jbHVkZS9oeXAvc3lzcmVnLXNyLmgKPj4+IGIvYXJjaC9hcm02NC9rdm0vaHlwL2luY2x1 ZGUvaHlwL3N5c3JlZy1zci5oCj4+PiBpbmRleCBjY2U0M2JmZTE1OGYuLjk0ZDk3MzZmMDEzMyAx MDA2NDQKPj4+IC0tLSBhL2FyY2gvYXJtNjQva3ZtL2h5cC9pbmNsdWRlL2h5cC9zeXNyZWctc3Iu aAo+Pj4gKysrIGIvYXJjaC9hcm02NC9rdm0vaHlwL2luY2x1ZGUvaHlwL3N5c3JlZy1zci5oCj4+ PiBAQCAtNDUsNiArNDUsOCBAQCBzdGF0aWMgaW5saW5lIHZvaWQgX19zeXNyZWdfc2F2ZV9lbDFf c3RhdGUoc3RydWN0Cj4+PiBrdm1fY3B1X2NvbnRleHQgKmN0eHQpCj4+PiDCoMKgwqDCoCBjdHh0 X3N5c19yZWcoY3R4dCwgQ05US0NUTF9FTDEpwqDCoMKgID0gCj4+PiByZWFkX3N5c3JlZ19lbDEo U1lTX0NOVEtDVEwpOwo+Pj4gwqDCoMKgwqAgY3R4dF9zeXNfcmVnKGN0eHQsIFBBUl9FTDEpwqDC oMKgID0gcmVhZF9zeXNyZWdfcGFyKCk7Cj4+PiDCoMKgwqDCoCBjdHh0X3N5c19yZWcoY3R4dCwg VFBJRFJfRUwxKcKgwqDCoCA9IHJlYWRfc3lzcmVnKHRwaWRyX2VsMSk7Cj4+PiArwqDCoMKgIGlm IChzeXN0ZW1fc3VwcG9ydHNfbXRlKCkpCj4+PiArwqDCoMKgwqDCoMKgwqAgY3R4dF9zeXNfcmVn KGN0eHQsIFRGU1JfRUwxKSA9IHJlYWRfc3lzcmVnX2VsMShTWVNfVEZTUik7Cj4+IAo+PiBJIGFs cmVhZHkgYXNrZWQgZm9yIGl0LCBhbmQgSSdtIGdvaW5nIHRvIGFzayBmb3IgaXQgYWdhaW46Cj4+ IE1vc3Qgb2YgdGhlIHN5c3JlZyBzYXZlL3Jlc3RvcmUgaXMgZ3VhcmRlZCBieSBhIHBlci12Y3B1 IGNoZWNrCj4+IChIQ1JfRUwyLkFUQSksIHdoaWxlIHRoaXMgb25lIGlzIHVuY29uZGl0aW9uYWxs eSBzYXZlZC9yZXN0b3JlCj4+IGlmIHRoZSBob3N0IGlzIE1URSBjYXBhYmxlLiBXaHkgaXMgdGhh dCBzbz8KPiAKPiBTb3JyeSwgSSB0aG91Z2h0IHlvdXIgY29uY2VybiB3YXMgZm9yIHJlZ2lzdGVy cyB0aGF0IGFmZmVjdCB0aGUgaG9zdAo+IChhcyB0aGV5IGFyZSBvYnZpb3VzbHkgbW9yZSBwZXJm b3JtYW5jZSBjcml0aWNhbCBhcyB0aGV5IGFyZSBoaXQgb24KPiBldmVyeSBndWVzdCBleGl0KS4g QWx0aG91Z2ggSSBndWVzcyB0aGF0J3MgaW5jb3JyZWN0IGZvciBuVkhFIHdoaWNoIGlzCj4gd2hh dCBhbGwgdGhlIGNvb2wga2lkcyB3YW50IG5vdyA7KQoKSSB0aGluayB3ZSB3YW50IGJvdGggY29y cmVjdG5lc3MgKmFuZCogcGVyZm9ybWFuY2UsIGZvciBib3RoIFZIRQphbmQgblZIRS4gVGhpbmdz IGxpa2UgRUwwIHJlZ2lzdGVycyBzaG91bGQgYmUgYWJsZSB0byBiZSBtb3ZlZAp0byBsb2FkL3B1 dCBvbiBhbGwgaW1wbGVtZW50YXRpb25zLCBhbmQgdGhlIGNvcnJlY3Qgc3dpdGNoaW5nCmJlIGRv bmUgYXQgdGhlIHJpZ2h0IHNwb3Qgb25seSB3aGVuIHJlcXVpcmVkLgoKVGhhbmtzLAoKICAgICAg ICAgTS4KLS0gCkphenogaXMgbm90IGRlYWQuIEl0IGp1c3Qgc21lbGxzIGZ1bm55Li4uCgpfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2Vy bmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0 cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVs Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97481C433E6 for ; Thu, 4 Feb 2021 14:59:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6082064F65 for ; Thu, 4 Feb 2021 14:59:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237095AbhBDO7X (ORCPT ); Thu, 4 Feb 2021 09:59:23 -0500 Received: from mail.kernel.org ([198.145.29.99]:45908 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236957AbhBDO44 (ORCPT ); Thu, 4 Feb 2021 09:56:56 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7BEA264D9F; Thu, 4 Feb 2021 14:56:15 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1l7g3J-00C1uA-9o; Thu, 04 Feb 2021 14:56:13 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Date: Thu, 04 Feb 2021 14:56:13 +0000 From: Marc Zyngier To: Steven Price Cc: Catalin Marinas , Will Deacon , James Morse , Julien Thierry , Suzuki K Poulose , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Martin , Mark Rutland , Thomas Gleixner , qemu-devel@nongnu.org, Juan Quintela , "Dr. David Alan Gilbert" , Richard Henderson , Peter Maydell , Haibo Xu , Andrew Jones Subject: Re: [PATCH v7 1/3] arm64: kvm: Save/restore MTE registers In-Reply-To: References: <20210115152811.8398-1-steven.price@arm.com> <20210115152811.8398-2-steven.price@arm.com> User-Agent: Roundcube Webmail/1.4.10 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: steven.price@arm.com, catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave.Martin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, qemu-devel@nongnu.org, quintela@redhat.com, dgilbert@redhat.com, richard.henderson@linaro.org, peter.maydell@linaro.org, Haibo.Xu@arm.com, drjones@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021-02-04 14:33, Steven Price wrote: > On 02/02/2021 15:36, Marc Zyngier wrote: >> On 2021-01-15 15:28, Steven Price wrote: >>> Define the new system registers that MTE introduces and context >>> switch >>> them. The MTE feature is still hidden from the ID register as it >>> isn't >>> supported in a VM yet. >>> >>> Signed-off-by: Steven Price >>> --- >>>  arch/arm64/include/asm/kvm_host.h          |  4 ++ >>>  arch/arm64/include/asm/kvm_mte.h           | 74 >>> ++++++++++++++++++++++ >>>  arch/arm64/include/asm/sysreg.h            |  3 +- >>>  arch/arm64/kernel/asm-offsets.c            |  3 + >>>  arch/arm64/kvm/hyp/entry.S                 |  7 ++ >>>  arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h |  4 ++ >>>  arch/arm64/kvm/sys_regs.c                  | 14 ++-- >>>  7 files changed, 104 insertions(+), 5 deletions(-) >>>  create mode 100644 arch/arm64/include/asm/kvm_mte.h >>> >>> diff --git a/arch/arm64/include/asm/kvm_host.h >>> b/arch/arm64/include/asm/kvm_host.h >>> index 11beda85ee7e..51590a397e4b 100644 >>> --- a/arch/arm64/include/asm/kvm_host.h >>> +++ b/arch/arm64/include/asm/kvm_host.h >>> @@ -148,6 +148,8 @@ enum vcpu_sysreg { >>>      SCTLR_EL1,    /* System Control Register */ >>>      ACTLR_EL1,    /* Auxiliary Control Register */ >>>      CPACR_EL1,    /* Coprocessor Access Control */ >>> +    RGSR_EL1,    /* Random Allocation Tag Seed Register */ >>> +    GCR_EL1,    /* Tag Control Register */ >>>      ZCR_EL1,    /* SVE Control */ >>>      TTBR0_EL1,    /* Translation Table Base Register 0 */ >>>      TTBR1_EL1,    /* Translation Table Base Register 1 */ >>> @@ -164,6 +166,8 @@ enum vcpu_sysreg { >>>      TPIDR_EL1,    /* Thread ID, Privileged */ >>>      AMAIR_EL1,    /* Aux Memory Attribute Indirection Register */ >>>      CNTKCTL_EL1,    /* Timer Control Register (EL1) */ >>> +    TFSRE0_EL1,    /* Tag Fault Status Register (EL0) */ >>> +    TFSR_EL1,    /* Tag Fault Stauts Register (EL1) */ >> >> s/Stauts/Status/ >> >> Is there any reason why the MTE registers aren't grouped together? > > I has been under the impression this list is sorted by the encoding of > the system registers, although double checking I've screwed up the > order of TFSRE0_EL1/TFSR_EL1, and not all the other fields are sorted > that way. It grew organically, and was initially matching the original order of the save/restore sequence. This order has long disappeared with VHE, and this is essentially nothing more than a bag of indices (although NV does bring some order back to deal with VNCR-backed registers). [...] >>> diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h >>> b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h >>> index cce43bfe158f..94d9736f0133 100644 >>> --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h >>> +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h >>> @@ -45,6 +45,8 @@ static inline void __sysreg_save_el1_state(struct >>> kvm_cpu_context *ctxt) >>>      ctxt_sys_reg(ctxt, CNTKCTL_EL1)    = >>> read_sysreg_el1(SYS_CNTKCTL); >>>      ctxt_sys_reg(ctxt, PAR_EL1)    = read_sysreg_par(); >>>      ctxt_sys_reg(ctxt, TPIDR_EL1)    = read_sysreg(tpidr_el1); >>> +    if (system_supports_mte()) >>> +        ctxt_sys_reg(ctxt, TFSR_EL1) = read_sysreg_el1(SYS_TFSR); >> >> I already asked for it, and I'm going to ask for it again: >> Most of the sysreg save/restore is guarded by a per-vcpu check >> (HCR_EL2.ATA), while this one is unconditionally saved/restore >> if the host is MTE capable. Why is that so? > > Sorry, I thought your concern was for registers that affect the host > (as they are obviously more performance critical as they are hit on > every guest exit). Although I guess that's incorrect for nVHE which is > what all the cool kids want now ;) I think we want both correctness *and* performance, for both VHE and nVHE. Things like EL0 registers should be able to be moved to load/put on all implementations, and the correct switching be done at the right spot only when required. Thanks, M. -- Jazz is not dead. It just smells funny... From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D415C433DB for ; Thu, 4 Feb 2021 14:58:40 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6305264F64 for ; Thu, 4 Feb 2021 14:58:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6305264F64 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:42528 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7g5e-0007Ue-Hs for qemu-devel@archiver.kernel.org; Thu, 04 Feb 2021 09:58:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7g3R-0005O0-QJ for qemu-devel@nongnu.org; Thu, 04 Feb 2021 09:56:21 -0500 Received: from mail.kernel.org ([198.145.29.99]:57666) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7g3O-0007du-9B for qemu-devel@nongnu.org; Thu, 04 Feb 2021 09:56:21 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7BEA264D9F; Thu, 4 Feb 2021 14:56:15 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1l7g3J-00C1uA-9o; Thu, 04 Feb 2021 14:56:13 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Date: Thu, 04 Feb 2021 14:56:13 +0000 From: Marc Zyngier To: Steven Price Subject: Re: [PATCH v7 1/3] arm64: kvm: Save/restore MTE registers In-Reply-To: References: <20210115152811.8398-1-steven.price@arm.com> <20210115152811.8398-2-steven.price@arm.com> User-Agent: Roundcube Webmail/1.4.10 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: steven.price@arm.com, catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave.Martin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, qemu-devel@nongnu.org, quintela@redhat.com, dgilbert@redhat.com, richard.henderson@linaro.org, peter.maydell@linaro.org, Haibo.Xu@arm.com, drjones@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Received-SPF: pass client-ip=198.145.29.99; envelope-from=maz@kernel.org; helo=mail.kernel.org X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Peter Maydell , "Dr. David Alan Gilbert" , Andrew Jones , Haibo Xu , Suzuki K Poulose , qemu-devel@nongnu.org, Catalin Marinas , Juan Quintela , Richard Henderson , linux-kernel@vger.kernel.org, Dave Martin , James Morse , linux-arm-kernel@lists.infradead.org, Thomas Gleixner , Will Deacon , kvmarm@lists.cs.columbia.edu, Julien Thierry Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2021-02-04 14:33, Steven Price wrote: > On 02/02/2021 15:36, Marc Zyngier wrote: >> On 2021-01-15 15:28, Steven Price wrote: >>> Define the new system registers that MTE introduces and context >>> switch >>> them. The MTE feature is still hidden from the ID register as it >>> isn't >>> supported in a VM yet. >>> >>> Signed-off-by: Steven Price >>> --- >>>  arch/arm64/include/asm/kvm_host.h          |  4 ++ >>>  arch/arm64/include/asm/kvm_mte.h           | 74 >>> ++++++++++++++++++++++ >>>  arch/arm64/include/asm/sysreg.h            |  3 +- >>>  arch/arm64/kernel/asm-offsets.c            |  3 + >>>  arch/arm64/kvm/hyp/entry.S                 |  7 ++ >>>  arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h |  4 ++ >>>  arch/arm64/kvm/sys_regs.c                  | 14 ++-- >>>  7 files changed, 104 insertions(+), 5 deletions(-) >>>  create mode 100644 arch/arm64/include/asm/kvm_mte.h >>> >>> diff --git a/arch/arm64/include/asm/kvm_host.h >>> b/arch/arm64/include/asm/kvm_host.h >>> index 11beda85ee7e..51590a397e4b 100644 >>> --- a/arch/arm64/include/asm/kvm_host.h >>> +++ b/arch/arm64/include/asm/kvm_host.h >>> @@ -148,6 +148,8 @@ enum vcpu_sysreg { >>>      SCTLR_EL1,    /* System Control Register */ >>>      ACTLR_EL1,    /* Auxiliary Control Register */ >>>      CPACR_EL1,    /* Coprocessor Access Control */ >>> +    RGSR_EL1,    /* Random Allocation Tag Seed Register */ >>> +    GCR_EL1,    /* Tag Control Register */ >>>      ZCR_EL1,    /* SVE Control */ >>>      TTBR0_EL1,    /* Translation Table Base Register 0 */ >>>      TTBR1_EL1,    /* Translation Table Base Register 1 */ >>> @@ -164,6 +166,8 @@ enum vcpu_sysreg { >>>      TPIDR_EL1,    /* Thread ID, Privileged */ >>>      AMAIR_EL1,    /* Aux Memory Attribute Indirection Register */ >>>      CNTKCTL_EL1,    /* Timer Control Register (EL1) */ >>> +    TFSRE0_EL1,    /* Tag Fault Status Register (EL0) */ >>> +    TFSR_EL1,    /* Tag Fault Stauts Register (EL1) */ >> >> s/Stauts/Status/ >> >> Is there any reason why the MTE registers aren't grouped together? > > I has been under the impression this list is sorted by the encoding of > the system registers, although double checking I've screwed up the > order of TFSRE0_EL1/TFSR_EL1, and not all the other fields are sorted > that way. It grew organically, and was initially matching the original order of the save/restore sequence. This order has long disappeared with VHE, and this is essentially nothing more than a bag of indices (although NV does bring some order back to deal with VNCR-backed registers). [...] >>> diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h >>> b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h >>> index cce43bfe158f..94d9736f0133 100644 >>> --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h >>> +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h >>> @@ -45,6 +45,8 @@ static inline void __sysreg_save_el1_state(struct >>> kvm_cpu_context *ctxt) >>>      ctxt_sys_reg(ctxt, CNTKCTL_EL1)    = >>> read_sysreg_el1(SYS_CNTKCTL); >>>      ctxt_sys_reg(ctxt, PAR_EL1)    = read_sysreg_par(); >>>      ctxt_sys_reg(ctxt, TPIDR_EL1)    = read_sysreg(tpidr_el1); >>> +    if (system_supports_mte()) >>> +        ctxt_sys_reg(ctxt, TFSR_EL1) = read_sysreg_el1(SYS_TFSR); >> >> I already asked for it, and I'm going to ask for it again: >> Most of the sysreg save/restore is guarded by a per-vcpu check >> (HCR_EL2.ATA), while this one is unconditionally saved/restore >> if the host is MTE capable. Why is that so? > > Sorry, I thought your concern was for registers that affect the host > (as they are obviously more performance critical as they are hit on > every guest exit). Although I guess that's incorrect for nVHE which is > what all the cool kids want now ;) I think we want both correctness *and* performance, for both VHE and nVHE. Things like EL0 registers should be able to be moved to load/put on all implementations, and the correct switching be done at the right spot only when required. Thanks, M. -- Jazz is not dead. It just smells funny...