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Fri, 13 Nov 2026 13:52:42 -0800 (PST) Received: from [10.67.48.245] ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-37956bb0c40sm11022781eec.28.2026.11.13.13.52.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Nov 2026 13:52:41 -0800 (PST) Message-ID: Date: Fri, 13 Nov 2026 13:52:40 -0800 X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: (subset) [PATCH v6 0/4] MIPS: CI20: Enable SMP with two CPUs To: Brian Masney , linux-mips@vger.kernel.org Cc: Thomas Bogendoerfer , Paul Burton , Paul Cercueil , Stephen Boyd , Brian Masney , Jerome Brunet , =?UTF-8?B?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, hns@goldelico.com, paul@boddie.org.uk References: <20261113190836.470937-1-f.fainelli@gmail.com> <179460306211.1364508.5876481329838567672.b4-ty@b4> Content-Language: en-US, fr-FR From: Florian Fainelli In-Reply-To: <179460306211.1364508.5876481329838567672.b4-ty@b4> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/13/26 12:51, Brian Masney wrote: > > On Fri, 13 Nov 2026 11:08:32 -0800, Florian Fainelli wrote: >> MIPS: CI20: Enable SMP with two CPUs >> >> This patch series resurrects SMP support for the CI20 board. This was >> submitted back in 2020 by Zhou Yanjie. >> >> Changes in v6: >> >> [...] > > Applied, thanks! > > [1/4] clk: ingenic: Poll JZ4780 CPU1 power status atomically > https://git.kernel.org/clk/linux/c/2c45b7e1e2f7 > > Best regards, Thanks Brian, I will remove that patch from future submissions. -- Florian