From mboxrd@z Thu Jan 1 00:00:00 1970
From: bugzilla-daemon@freedesktop.org
Subject: [Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout
setting UVD clocks!
Date: Wed, 28 Jan 2015 20:44:25 +0000
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https://bugs.freedesktop.org/show_bug.cgi?id=3D73378
--- Comment #18 from Chernovsky Oleg ---
(In reply to Alex Deucher from comment #16)
> (In reply to Christian K=C3=B6nig from comment #14)
> > (In reply to =C3=96yvind Saether from comment #13)
> > > on 3.18.1, could this be because the card is factory overclocked?
> >=20
> > Yes, that's possible. If you activate UVD you must downclock the system
> > clock for it to work reliable. Not sure if we have implemented that
> > correctly for SI.
>=20
> We already handle it. SI has UVD power states which also include validat=
ed
> sclk and mclk levels that are often different than the performance state.=
=20
> The driver switches to those states when UVD is used. At driver load time
> (when the ring and IB tests are done), the hw is still in the boot state
> (which has really low clocks) anyway.
Hm-m, just tried drm-next-3.20 branch and:
[ 365.200918] [drm:radeon_uvd_send_upll_ctlreq [radeon]] *ERROR* Timeout
setting UVD clocks!
[ 365.200922] [drm:uvd_v1_0_ib_test [radeon]] *ERROR* radeon: failed to ra=
ise
UVD clocks (-110).
[ 365.200928] [drm:radeon_ib_ring_tests [radeon]] *ERROR* radeon: failed
testing IB on ring 5 (-110).
Both on cold start and resume from suspend, Pitcairn, Mesa 10.4.3
Ah yes, the card is factory overclocked (at least box states so)
It's not very painful for me but if I can help somehow, I'm in
--=20
You are receiving this mail because:
You are the assignee for the bug.
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Date: Wed, 28 Jan 2015 20:44:25 +0000
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Commen=
t # 18
on bug 73378<=
/a>
from =
Chernovsky Oleg
(In reply to Alex Deucher from comment #16)
> (In reply to Christian K=C3=B6nig from comment #14)
> > (In reply to =C3=96yvind Saether from comment #13)
> > > on 3.18.1, could this be because the card is factory overclo=
cked?
> >=20
> > Yes, that's possible. If you activate UVD you must downclock the =
system
> > clock for it to work reliable. Not sure if we have implemented th=
at
> > correctly for SI.
>=20
> We already handle it. SI has UVD power states which also include vali=
dated
> sclk and mclk levels that are often different than the performance sta=
te.=20
> The driver switches to those states when UVD is used. At driver load =
time
> (when the ring and IB tests are done), the hw is still in the boot sta=
te
> (which has really low clocks) anyway.
Hm-m, just tried drm-next-3.20 branch and:
[ 365.200918] [drm:radeon_uvd_send_upll_ctlreq [radeon]] *ERROR* Timeout
setting UVD clocks!
[ 365.200922] [drm:uvd_v1_0_ib_test [radeon]] *ERROR* radeon: failed to ra=
ise
UVD clocks (-110).
[ 365.200928] [drm:radeon_ib_ring_tests [radeon]] *ERROR* radeon: failed
testing IB on ring 5 (-110).
Both on cold start and resume from suspend, Pitcairn, Mesa 10.4.3
Ah yes, the card is factory overclocked (at least box states so)
It's not very painful for me but if I can help somehow, I'm in
You are receiving this mail because:
=20=20=20=20=20=20
- You are the assignee for the bug.
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