From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon-CC+yJ3UmIYqDUpFQwHEjaQ@public.gmane.org Subject: [Bug 75985] [NVC1] HDMI audio device only visible after rescan Date: Sun, 11 Mar 2018 12:53:50 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1737597479==" Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: nouveau-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Nouveau" To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org List-Id: nouveau.vger.kernel.org --===============1737597479== Content-Type: multipart/alternative; boundary="15207728310.0Fb8.14688" Content-Transfer-Encoding: 7bit --15207728310.0Fb8.14688 Date: Sun, 11 Mar 2018 12:53:50 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated https://bugs.freedesktop.org/show_bug.cgi?id=3D75985 --- Comment #68 from Lukas Wunner --- Created attachment 137989 --> https://bugs.freedesktop.org/attachment.cgi?id=3D137989&action=3Dedit Patch to simulate hidden HDA on systems which normally expose it This is a quick & dirty hack to hide the HDA controller in the EFI stub. It= can be used to simulate a hidden HDA controller on systems which normally expose it. Register 0x488 is written for any PCI device that has a ROM. On my mach= ine that happens to only be the case for the Nvidia GPU. If I boot my system with this patch applied, the HDA controller is not enumerated and invoking lspci on the GPU shows that the multifunction bit is cleared, as is bit 25 at offset 0x488. Applying the three other patches I've attached to this bugzilla on top resu= lts in the HDA controller being enumerated again. So the patches seem to work as intended. One interesting behavior I've noticed though: If I hide the HDA in the EFI = stub and do not expose it with a PCI quirk, putting the GPU into D3cold and back into D0 causes the multifunction bit to be set, same for bit 25 at offset 0x488, even though the bits were cleared before the GPU went into D3cold. I don't see anything in the ACPI tables that bit 25 is written, I'm rather un= der the impression that the GPU has some non-volatile memory where the vendor preconfigures bits that are restored when the device comes out of power-on reset. But because the PCI quirk is also executed on resume of the GPU, we should have that covered. --=20 You are receiving this mail because: You are the assignee for the bug.= --15207728310.0Fb8.14688 Date: Sun, 11 Mar 2018 12:53:51 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated

Commen= t # 68 on bug 75985<= /a> from Lukas Wunner
Created   [review]
Patch to simulate hidden HDA on systems which normally expose it

This is a quick & dirty hack to hide the HDA controller in the EFI stub=
. It can
be used to simulate a hidden HDA controller on systems which normally expose
it. Register 0x488 is written for any PCI device that has a ROM. On my mach=
ine
that happens to only be the case for the Nvidia GPU.

If I boot my system with this patch applied, the HDA controller is not
enumerated and invoking lspci on the GPU shows that the multifunction bit is
cleared, as is bit 25 at offset 0x488.

Applying the three other patches I've attached to this bugzilla on top resu=
lts
in the HDA controller being enumerated again. So the patches seem to work as
intended.

One interesting behavior I've noticed though: If I hide the HDA in the EFI =
stub
and do not expose it with a PCI quirk, putting the GPU into D3cold and back
into D0 causes the multifunction bit to be set, same for bit 25 at offset
0x488, even though the bits were cleared before the GPU went into D3cold. I
don't see anything in the ACPI tables that bit 25 is written, I'm rather un=
der
the impression that the GPU has some non-volatile memory where the vendor
preconfigures bits that are restored when the device comes out of power-on
reset. But because the PCI quirk is also executed on resume of the GPU, we
should have that covered.


You are receiving this mail because:
  • You are the assignee for the bug.
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