[Bug 91861] [Radeon RS780] Blank screen (no signal) on HDMI after boot in 3.15 & later

[bugzilla-daemon@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=91861

--- Comment #7 from Christian König <deathsimple@vodafone.de> ---
(In reply to Mike S. from comment #6)
> I can confirm that the patch
> https://bugzilla.kernel.org/attachment.cgi?id=163891 to cap ref_div to 7
> fixes the problem on my RS780. I did the test on kernel 3.18.3. Note that I
> also cast the number 7 in the min() to unsigned to avoid a compiler warning.

Thanks for testing.

> I'd also like to ask a question, please. With this patch, the GPU divider
> values are now running at:
> 
> 148500 - 148490, pll dividers - fb: 580.7 ref: 7, post 8
> 
> while on 3.14 they were:
> 
> 14851, pll dividers - fb: 145.2 ref: 2, post: 7
> 
> These new values produce a marginally different dot clock rate (the old
> debug msg displayed the value 10x less than the new one), but the difference
> is tiny, and probably doesn't make any practical difference.

It does make quite a difference, that's why I've added the new code in the
first place. Some people had problems with the old one resulting in unstable
signals and audio/video desync after a while.

> Other than the dot clock, do the values of the 3 dividers affect anything
> else in the GPU? Are there any advantages or disadvantages running the FB
> and REF substantially higher (as they are now)?
When you use higher dividers in a PLL you can get closer to the desired
frequency, but at the cost of higher jitter. The trick is to stay within the
limits of the PLL. For example the VCO shouldn't get to fast otherwise the
input voltage gets to high, the feedback divider shouldn't get to high cause
otherwise the jitter is to high for the PLL to follow etc...

We most likely have an undocumented limit on the input frequency here,
otherwise limiting the reference divider won't have such an effect.

Christian.

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