I'm the main developer of Ogre 2.1
We're trying our demos in latest Mesa:
I've built Mesa from scratch. Tried commits git-edfc17a (current head of br=
anch
12.0) and commit 17f1c49b9ad05af4f6482f6fa950e5dcc1a779d1 (current head of
master branch)
Almost all of them work except for the compute shader based ones (Googling
around it appears for Southern Island radeon it could be buggy so it was tu=
rned
off. Not 100% sure but I think that's what's happening).
Anyway, not a big deal on that. I understand the Mesa team considers that W=
IP.
Move on.
However our Forward3D demo was glitching and I didn't know why. I've
investigated the problem and located it:
* glGetIntegerv w/ GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT is returning 4, should
return 256 for my HW (GCN 1.0 AMD Radeon HD 7770 Southern Islands).
* glGetIntegerv w/ GL_TEXTURE_BUFFER_OFFSET_ALIGNMENT is returning 4, should
return 256 for my HW.
In both cases "256" is what Windows drivers return btw, including=
fglrx on
Linux.
When aligned to 4 bytes; the following worked correctly:
glTexBufferRange( GL_TEXTURE_BUFFER, GL_R32UI, boName,
offsetAlignedTo4ButNotTo256, sizeBytes );
uniform usamplerBuffer f3dGrid;
uint numLightsInGrid =3D texelFetch( f3dGrid, int(sampleOffset) ).x;
But the following did not:
glTexBufferRange( GL_TEXTURE_BUFFER, GL_RGBA32F, boName,
offsetAlignedTo4ButNotTo256, sizeBytes );
uniform samplerBuffer f3dLightList;
vec4 values =3D texelFetch( f3dLightList, int(sampleOffset) ).x;
The output of the latter was flickering garbage. When I forced 256 byte
alignment, it worked as expected.
I consider this a critical issue because I suspect it's causing subtle prob=
lems
with a lot of titles whose buffer offsets don't start at 0.
I believe NVIDIA GPUs also require buffer offsets of 256. I don't know about
Intel cards.