From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 99967] RX 480 sclk clock speed lowers when under load Date: Sun, 26 Feb 2017 01:03:43 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1079797896==" Return-path: Received: from culpepper.freedesktop.org (culpepper.freedesktop.org [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id 459126E253 for ; Sun, 26 Feb 2017 01:03:43 +0000 (UTC) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============1079797896== Content-Type: multipart/alternative; boundary="14880710230.7E8a10f5b.15105"; charset="UTF-8" --14880710230.7E8a10f5b.15105 Date: Sun, 26 Feb 2017 01:03:43 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated https://bugs.freedesktop.org/show_bug.cgi?id=3D99967 --- Comment #1 from Christoph Haag --- Created attachment 129918 --> https://bugs.freedesktop.org/attachment.cgi?id=3D129918&action=3Dedit screenshot with echo auto > power_dpm_force_performance_level On "auto" the sclk clock speeds resets by itself properly, but the clock sp= eed under load is not raised to the levels where it should be, for example when running furmark all bars in radeontop show >95% load, yet the sclk is at le= vel 1: 608Mhz. --=20 You are receiving this mail because: You are the assignee for the bug.= --14880710230.7E8a10f5b.15105 Date: Sun, 26 Feb 2017 01:03:43 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated

Comment= # 1 on bug 99967<= /a> from Christoph Haag 
Created attachment 129918 [details]
screenshot with echo auto > power_dpm_force_performance_level

On "auto" the sclk clock speeds resets by itself properly, but th=
e clock speed
under load is not raised to the levels where it should be, for example when
running furmark all bars in radeontop show >95% load, yet the sclk is at=
 level
1: 608Mhz.

You are receiving this mail because:
  • You are the assignee for the bug.
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