From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Michael Tokarev <mjt@tls.msk.ru>,
Peter Maydell <peter.maydell@linaro.org>,
alistair23@gmail.com
Cc: qemu-devel@nongnu.org, Andrew Jones <ajones@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>,
qemu-stable <qemu-stable@nongnu.org>
Subject: Re: [PULL 47/56] target/riscv/kvm: add scounteren CSR
Date: Sat, 25 Oct 2025 21:36:51 -0300 [thread overview]
Message-ID: <c01b9130-e706-4f56-b67a-653130f7ee01@ventanamicro.com> (raw)
In-Reply-To: <7fe9bec3-43f5-4d28-9efa-5d499335baf8@tls.msk.ru>
On 10/25/25 1:45 PM, Michael Tokarev wrote:
> On 10/24/25 19:17, Daniel Henrique Barboza wrote:
>>
>>
>> On 10/24/25 10:43 AM, Peter Maydell wrote:
>>> On Mon, 19 May 2025 at 05:25, <alistair23@gmail.com> wrote:
>>>>
>>>> From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>>>>
>>>> Add support for the scounteren KVM CSR. Note that env->scounteren is a
>>>> 32 bit and all KVM CSRs are target_ulong, so scounteren will be capped
>>>> to 32 bits read/writes.
>>>>
>>>> Reported-by: Andrew Jones <ajones@ventanamicro.com>
>>>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>>>> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>>>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>>>> Message-ID: <20250429124421.223883-10-dbarboza@ventanamicro.com>
>>>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>>>> ---
>>>> target/riscv/kvm/kvm-cpu.c | 2 ++
>>>> 1 file changed, 2 insertions(+)
>>>>
>>>> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
>>>> index ca171d5457..82f9728636 100644
>>>> --- a/target/riscv/kvm/kvm-cpu.c
>>>> +++ b/target/riscv/kvm/kvm-cpu.c
>>>> @@ -251,6 +251,7 @@ static KVMCPUConfig kvm_csr_cfgs[] = {
>>>> KVM_CSR_CFG("stval", stval, RISCV_CSR_REG(stval)),
>>>> KVM_CSR_CFG("sip", mip, RISCV_CSR_REG(sip)),
>>>> KVM_CSR_CFG("satp", satp, RISCV_CSR_REG(satp)),
>>>> + KVM_CSR_CFG("scounteren", scounteren, RISCV_CSR_REG(scounteren)),
>>>> KVM_CSR_CFG("senvcfg", senvcfg, RISCV_CSR_REG(senvcfg)),
>>>> };
>>>>
>>>> @@ -701,6 +702,7 @@ static void kvm_riscv_reset_regs_csr(CPURISCVState *env)
>>>> env->stval = 0;
>>>> env->mip = 0;
>>>> env->satp = 0;
>>>> + env->scounteren = 0;
>>>> env->senvcfg = 0;
>>>> }
>>>
>>> Hi -- this came up in a conversation on IRC. Does this new
>>> CPU state field need migration support adding in machine.c ?
>>
>>
>> Hmm, I believe it already has, doesn't it?
>>
>> target/riscv/machine.c:
>>
>>
>> const VMStateDescription vmstate_riscv_cpu = {
>> .name = "cpu",
>> .version_id = 10,
>> .minimum_version_id = 10,
>> .post_load = riscv_cpu_post_load,
>> .fields = (const VMStateField[]) {
>> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
>> (...)
>> VMSTATE_UINT32(env.scounteren, RISCVCPU), <-------
>>
>>
>> Or are you referring to something else like post_load callbacks and so on? Thanks,
>
> In this case, can or should this change be picked up for
> qemu-stable (in this case, 10.0.x)?
>
> Not that it's hugely important, but some subsequent patches
> in this area would apply cleanly if I'll pick this one and
> also senvcfg one (86b8c3821496).
Go ahead, but to pick those you'll need to also pick these:
[PULL 44/56] target/riscv/kvm: do not read unavailable CSRs
[PULL 46/56] target/riscv/kvm: read/write KVM regs via env size
Otherwise you might introduce bugs. Thanks,
Daniel
>
> Thanks,
>
> /mjt
next prev parent reply other threads:[~2025-10-26 0:37 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-19 4:04 [PULL 00/56] riscv-to-apply queue alistair23
2025-05-19 4:04 ` [PULL 01/56] hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structure alistair23
2025-05-19 4:04 ` [PULL 02/56] hw/riscv/virt-acpi-build: Add support for RIMT alistair23
2025-05-19 4:05 ` [PULL 03/56] target/riscv: pmp: don't allow RLB to bypass rule privileges alistair23
2025-05-19 4:05 ` [PULL 04/56] target/riscv: pmp: move Smepmp operation conversion into a function alistair23
2025-05-19 4:05 ` [PULL 05/56] target/riscv: pmp: fix checks on writes to pmpcfg in Smepmp MML mode alistair23
2025-05-19 4:05 ` [PULL 06/56] target/riscv: pmp: exit csr writes early if value was not changed alistair23
2025-05-19 4:05 ` [PULL 07/56] target/riscv: pmp: remove redundant check in pmp_is_locked alistair23
2025-05-19 4:05 ` [PULL 08/56] Generate strided vector loads/stores with tcg nodes alistair23
2025-05-19 4:05 ` [PULL 09/56] hw/misc: Add MPFS system reset support alistair23
2025-05-19 4:05 ` [PULL 10/56] hw/riscv: More flexible FDT placement for MPFS alistair23
2025-05-19 4:05 ` [PULL 11/56] hw/riscv: Make FDT optional " alistair23
2025-05-19 4:05 ` [PULL 12/56] hw/riscv: Allow direct start of kernel " alistair23
2025-05-19 4:05 ` [PULL 13/56] hw/riscv: Configurable MPFS CLINT timebase freq alistair23
2025-05-19 4:05 ` [PULL 14/56] hw/riscv: microchip_pfsoc: Rework documentation alistair23
2025-05-19 4:05 ` [PULL 15/56] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores alistair23
2025-05-19 4:05 ` [PULL 16/56] Expand the probe_pages helper function to handle probe flags alistair23
2025-05-19 4:05 ` [PULL 17/56] hw/riscv: Fix type conflict of GLib function pointers alistair23
2025-05-19 4:05 ` [PULL 18/56] target/riscv: fix endless translation loop on big endian systems alistair23
2025-05-19 4:05 ` [PULL 19/56] common-user/host/riscv: use tail pseudoinstruction for calling tail alistair23
2025-05-19 4:05 ` [PULL 20/56] target/riscv: rvv: Source vector registers cannot overlap mask register alistair23
2025-05-19 4:05 ` [PULL 21/56] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS alistair23
2025-05-19 4:05 ` [PULL 22/56] target/riscv: rvv: Apply vext_check_input_eew to vrgather instructions to check mismatched input EEWs encoding constraint alistair23
2025-05-19 4:05 ` [PULL 23/56] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions alistair23
2025-05-19 4:05 ` [PULL 24/56] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions alistair23
2025-05-19 4:05 ` [PULL 25/56] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX) alistair23
2025-05-19 4:05 ` [PULL 26/56] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV) alistair23
2025-05-19 4:05 ` [PULL 27/56] target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instructions alistair23
2025-05-19 4:05 ` [PULL 28/56] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions alistair23
2025-05-19 4:05 ` [PULL 29/56] target/riscv: Fix the rvv reserved encoding of unmasked instructions alistair23
2025-05-19 4:05 ` [PULL 30/56] target/riscv: Fix vslidedown with rvv_ta_all_1s alistair23
2025-05-19 4:05 ` [PULL 31/56] MAINTAINERS: Add common-user/host/riscv to RISC-V section alistair23
2025-05-19 4:05 ` [PULL 32/56] target/riscv: Pass ra to riscv_csr_write_fn alistair23
2025-05-19 4:05 ` [PULL 33/56] target/riscv: Pass ra to riscv_csrrw_do64 alistair23
2025-05-19 4:05 ` [PULL 34/56] target/riscv: Pass ra to riscv_csrrw_do128 alistair23
2025-05-19 4:05 ` [PULL 35/56] target/riscv: Pass ra to riscv_csrrw alistair23
2025-05-19 4:05 ` [PULL 36/56] target/riscv: Pass ra to riscv_csrrw_i128 alistair23
2025-05-19 4:05 ` [PULL 37/56] target/riscv: Move insn_len to internals.h alistair23
2025-05-19 4:05 ` [PULL 38/56] target/riscv: Fix write_misa vs aligned next_pc alistair23
2025-05-19 4:05 ` [PULL 39/56] target/riscv/kvm: minor fixes/tweaks alistair23
2025-05-19 4:05 ` [PULL 40/56] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg() alistair23
2025-05-19 4:05 ` [PULL 41/56] target/riscv/kvm: turn u32/u64 reg functions into macros alistair23
2025-05-19 4:05 ` [PULL 42/56] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro alistair23
2025-05-19 4:05 ` [PULL 43/56] target/riscv/kvm: add kvm_csr_cfgs[] alistair23
2025-05-19 4:05 ` [PULL 44/56] target/riscv/kvm: do not read unavailable CSRs alistair23
2025-05-19 4:05 ` [PULL 45/56] target/riscv/kvm: add senvcfg CSR alistair23
2025-05-19 4:05 ` [PULL 46/56] target/riscv/kvm: read/write KVM regs via env size alistair23
2025-05-19 4:05 ` [PULL 47/56] target/riscv/kvm: add scounteren CSR alistair23
2025-10-24 13:43 ` Peter Maydell
2025-10-24 16:17 ` Daniel Henrique Barboza
2025-10-24 16:31 ` Peter Maydell
2025-10-25 16:45 ` Michael Tokarev
2025-10-26 0:36 ` Daniel Henrique Barboza [this message]
2025-10-26 7:15 ` Michael Tokarev
2025-05-19 4:05 ` [PULL 48/56] hw/riscv/virt.c: enforce s->memmap use in machine_init() alistair23
2025-05-19 4:05 ` [PULL 49/56] hw/riscv/virt.c: remove trivial virt_memmap references alistair23
2025-05-19 4:05 ` [PULL 50/56] hw/riscv/virt.c: use s->memmap in virt_machine_done() alistair23
2025-05-19 4:05 ` [PULL 51/56] hw/riscv/virt.c: add 'base' arg in create_fw_cfg() alistair23
2025-05-19 4:05 ` [PULL 52/56] hw/riscv/virt.c: use s->memmap in create_fdt() path alistair23
2025-05-19 4:05 ` [PULL 53/56] hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path alistair23
2025-05-19 4:05 ` [PULL 54/56] hw/riscv/virt.c: use s->memmap in create_fdt_virtio() alistair23
2025-05-19 4:05 ` [PULL 55/56] hw/riscv/virt.c: use s->memmap in finalize_fdt() functions alistair23
2025-05-19 4:05 ` [PULL 56/56] hw/riscv/virt.c: remove 'long' casts in fmt strings alistair23
2025-05-19 21:17 ` [PULL 00/56] riscv-to-apply queue Stefan Hajnoczi
2025-05-20 5:08 ` Michael Tokarev
2025-05-20 5:47 ` Alistair Francis
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