From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE791C4743C for ; Mon, 21 Jun 2021 23:14:45 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 526CA6023D for ; Mon, 21 Jun 2021 23:14:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 526CA6023D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=tachyum.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:53114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvT7s-0007Pi-2a for qemu-devel@archiver.kernel.org; Mon, 21 Jun 2021 19:14:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvT6S-0006iK-Of for qemu-devel@nongnu.org; Mon, 21 Jun 2021 19:13:16 -0400 Received: from mx1.tachyum.com ([66.160.133.170]:40939) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvT6Q-0002Ay-Uh for qemu-devel@nongnu.org; Mon, 21 Jun 2021 19:13:16 -0400 Received: by mx1.tachyum.com (Postfix, from userid 1000) id B24821005693; Mon, 21 Jun 2021 16:13:11 -0700 (PDT) Received: from THQ-EX1.tachyum.com (unknown [10.7.1.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx1.tachyum.com (Postfix) with ESMTPS id 32514100D44E for ; Mon, 21 Jun 2021 16:13:11 -0700 (PDT) Received: from THQ-EX3.tachyum.com (10.7.1.26) by THQ-EX1.tachyum.com (10.7.1.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 21 Jun 2021 16:13:11 -0700 Received: from THQ-EX1.tachyum.com (10.7.1.6) by THQ-EX3.tachyum.com (10.7.1.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 21 Jun 2021 16:13:11 -0700 Received: from THQ-EX1.tachyum.com ([10.7.1.6]) by THQ-EX1.tachyum.com ([10.7.1.6]) with mapi id 15.01.2176.014; Mon, 21 Jun 2021 16:13:11 -0700 From: Michael Morrell To: "qemu-devel@nongnu.org" Subject: RE: Denormal input handling Thread-Topic: Denormal input handling Thread-Index: AddSVLVuQ70cTMk8SjeoZZpZvpdwcwUnLwIA Date: Mon, 21 Jun 2021 23:13:11 +0000 Message-ID: References: <30eafc8be31446f9aecbc40f487467e1@tachyum.com> In-Reply-To: <30eafc8be31446f9aecbc40f487467e1@tachyum.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.7.100.197] Content-Type: multipart/alternative; boundary="_000_c021f386dcfb49aca2ab0c01f66bccc2tachyumcom_" MIME-Version: 1.0 Received-SPF: pass client-ip=66.160.133.170; envelope-from=mmorrell@tachyum.com; helo=mx1.tachyum.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, HTML_MESSAGE=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --_000_c021f386dcfb49aca2ab0c01f66bccc2tachyumcom_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I have another couple of thoughts around input denormal handling. The first is straightforward. I noticed that the Aarch64 port doesn't repo= rt input denormals (I could not find any code which sets the IDC bit in the= FPSR). I found code in the arm (not aarch64) port that sets other bits li= ke IXC, but nothing for IDC. Is that simply because no one has bothered t= o add this support? The second concerns support for cases where multiple exception conditions o= ccur. I had originally thought that denormal input handling would be orth= ogonal to everything else and so a case like "sNaN + denorm" would set bot= h the invalid and input denormal flags or "denorm / 0" would set both idivd= e by zero and input denormal, but I don't think that is true for at least s= ome architectures. Perhaps some specialization is needed here? Michael --_000_c021f386dcfb49aca2ab0c01f66bccc2tachyumcom_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

I have another couple of thoughts around input denor= mal handling.

 

The first is straightforward.  I noticed that t= he Aarch64 port doesn't report input denormals (I could not find any code w= hich sets the IDC bit in the FPSR).  I found code in the arm (not aarc= h64) port that sets other bits like IXC, but nothing for IDC.   Is that simply because no one has bothered to= add this support?

 

The second concerns support for cases where multiple= exception conditions occur.   I had originally thought that deno= rmal input handling would be orthogonal to everything else and so a case li= ke "sNaN  + denorm" would set both the invalid and input denormal flags or "denorm / 0" would set both idivde b= y zero and input denormal, but I don't think that is true for at least some= architectures.  Perhaps some specialization is needed here?

 

  Michael

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