Re: [PATCH v2 2/2] drm/i915/ltphy: Fix SSC Enablement bit in PORT_CLOCK_CTL

["Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>]

On 7/1/2026 2:45 PM, Suraj Kandpal wrote:
> According to Bspec we only need to write SSC Enable PLL A bit
> and leave PLL B bit alone in PORT_CLOCK_CTL Register.
>
> Fixes: 3383ba2479f7 ("drm/i915/ltphy: Enable SSC during port clock programming")

Checks out with Bspec: 74667, 74492

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_lt_phy.c | 6 +-----
>   1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 956181f80d35..8fc6d230493f 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1223,11 +1223,7 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
>   	else
>   		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
>   
> -	 /* DP2.0 10G and 20G rates enable MPLLA*/
> -	if (port_clock == 1000000 || port_clock == 2000000)
> -		val |= XELPDP_SSC_ENABLE_PLLA;
> -	else
> -		val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> +	val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
>   
>   	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
>   		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |