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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e8f442129sm34884895e9.28.2026.05.13.00.15.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 May 2026 00:15:31 -0700 (PDT) Message-ID: Date: Wed, 13 May 2026 09:15:30 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: target/riscv: rdcycleh problem Content-Language: en-US To: Antony Pavlov , Alistair Francis Cc: Alistair Francis , QEMU Developers , qemu-riscv , Daniel Henrique Barboza References: <9a6f4a8a-9917-4384-b36e-9eafe2461725@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 13/5/26 07:44, Antony Pavlov wrote: > On Wed, 13 May 2026 at 04:50, Alistair Francis wrote: >> >> On Tue, May 12, 2026 at 1:43 PM Philippe Mathieu-Daudé >> wrote: >>> >>> Cc'ing qemu-riscv@ list >>> >>> On 12/5/26 02:50, Antony Pavlov wrote: >>>> Hi! >>>> >>>> I use qemu-system-riscv32 v11.0.0 for running this code: >>>> >>>> 15258: c80025f3 rdcycleh a1 >>>> 1525c: c0002573 rdcycle a0 >>>> 15260: c80027f3 rdcycleh a5 >>>> 15264: fef59ae3 bne a1,a5,15258 >>>> >>>> The code is recommended by riscv specification for reading 64-bit >>>> cycle counter on 32-bit system (see >>>> https://docs.riscv.org/reference/isa/unpriv/counters.html#7-1-1-zicntr-extension-for-base-counters-and-timers >>>> for details). >>>> >>>> When running on qemu-system-riscv32 both the rdcycle and the rdcycleh >>>> instructions read low 32-bit of the cycle counter so the branch >>>> instruction always go to 15258. >>> >>> Interestingly I'm having similar 32/64 bit conversion issue with >>> the set of CSR functions in my single binary prototype due to this >>> target_ulong use. >>> >>>> >>>> This quick and dirty patch fixes my problem: >>>> >>>> --- a/target/riscv/csr.c >>>> +++ b/target/riscv/csr.c >>>> @@ -1389,8 +1389,11 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState >>>> *env, target_ulong *val, >>>> */ >>>> if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || >>>> riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { >>>> - *val = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) - >>>> + uint64_t t; >>>> + >>>> + t = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) - >>>> ctr_prev + ctr_val; >>>> + *val = extract64(t, start, length); >>>> } else { >>>> *val = ctr_val; >>>> } >>>> >>>> Have you any suggestion? >> >> Yeah, it looks like a bug using the `target_ulong` (which is only >> 32-bits on RV32). This is something that should be fixed, if you can >> send a patch that would be great > > I'll send the patch within a few days. As you said this change is "quick and dirty". I suppose what Alistair suggested is to replace 'target_ulong *' by 'uint64_t *' where relevant, doing the appropriate truncations when riscv_cpu_mxl(env) == MXL_RV32.