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d="scan'208";a="3035563" Received: from ettammin-mobl2.ger.corp.intel.com (HELO localhost) ([10.245.244.21]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2026 08:49:30 -0700 From: Jani Nikula To: Ville Syrjala , intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: Re: [PATCH 03/15] drm/i915/pfit: Stop using HAS_PCH_SPLIT() in confusing places In-Reply-To: <20261019135309.23578-4-ville.syrjala@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland References: <20261019135309.23578-1-ville.syrjala@linux.intel.com> <20261019135309.23578-4-ville.syrjala@linux.intel.com> Date: Mon, 19 Oct 2026 18:49:27 +0300 Message-ID: X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Intel-xe" X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, RCVD_IN_ZEN_BLOCKED_OPENDNS,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Mon, 19 Oct 2026, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Stop using HAS_PCH_SPLIT() in places that have nothing to > do with PCH. !HAS_GMCH is a more sensible thing top check for. *to Reviewed-by: Jani Nikula > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +- > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i91= 5/display/i9xx_wm.c > index 86d1c9f7f0ff..0233f5053d95 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_wm.c > +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c > @@ -4150,7 +4150,7 @@ static const struct intel_wm_funcs nop_funcs =3D { > void i9xx_wm_init(struct intel_display *display) > { > /* For FIFO watermark updates */ > - if (HAS_PCH_SPLIT(display)) { > + if (!HAS_GMCH(display)) { > ilk_setup_wm_latency(display); > display->wm.funcs =3D &ilk_wm_funcs; > } else if (display->platform.valleyview || display->platform.cherryview= ) { > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/d= rm/i915/display/intel_display.c > index 723dec35402a..d1440cc6dba4 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -6777,7 +6777,7 @@ static void intel_pipe_fastset(const struct intel_c= rtc_state *old_crtc_state, > if (DISPLAY_VER(display) >=3D 9) { > if (new_crtc_state->pfit.enabled) > skl_pfit_enable(new_crtc_state); > - } else if (HAS_PCH_SPLIT(display)) { > + } else if (!HAS_GMCH(display)) { > if (new_crtc_state->pfit.enabled) > ilk_pfit_enable(new_crtc_state); > else if (old_crtc_state->pfit.enabled) > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drive= rs/gpu/drm/i915/display/intel_display_debugfs.c > index 3e302f23f247..dba34f034785 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > @@ -96,7 +96,7 @@ static int i915_sr_status(struct seq_file *m, void *unu= sed) >=20=20 > if (DISPLAY_VER(display) >=3D 9) > /* no global SR status; inspect per-plane WM */; > - else if (HAS_PCH_SPLIT(display)) > + else if (!HAS_GMCH(display)) > sr_enabled =3D intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE; > else if (display->platform.i965gm || display->platform.g4x || > display->platform.i945g || display->platform.i945gm) --=20 Jani Nikula, Intel