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d="scan'208";a="179284639" Received: from unknown (HELO [172.28.180.93]) ([172.28.180.93]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2025 06:10:12 -0700 Message-ID: Date: Tue, 30 Sep 2025 15:10:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/5] tests/intel/xe_exec_reset: Add timeslice preempt test To: Matthew Brost , igt-dev@lists.freedesktop.org References: <20250923211333.766147-1-matthew.brost@intel.com> <20250923211333.766147-3-matthew.brost@intel.com> Content-Language: en-US From: "Bernatowicz, Marcin" In-Reply-To: <20250923211333.766147-3-matthew.brost@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" On 9/23/2025 11:13 PM, Matthew Brost wrote: > Add tests in which submit multiple preemptable spinners to same hardware > engine ensuring a cumulative longer timeout and validating the restart > paths in the DRM scheduler TDR (Timeout Detection and Recovery). > > v3: > - Spell out TDR (Kamal) > > Signed-off-by: Matthew Brost > --- > lib/xe/xe_legacy.c | 5 +++-- > tests/intel/xe_exec_reset.c | 25 +++++++++++++++++++++++-- > 2 files changed, 26 insertions(+), 4 deletions(-) > > diff --git a/lib/xe/xe_legacy.c b/lib/xe/xe_legacy.c > index 669ecff7aa..9d2da7f413 100644 > --- a/lib/xe/xe_legacy.c > +++ b/lib/xe/xe_legacy.c > @@ -12,6 +12,7 @@ > > /* Batch buffer element count, in number of dwords(u32) */ > #define BATCH_DW_COUNT 16 > +#define CANCEL (0x1 << 7) > #define PREEMPT (0x1 << 6) > #define CAT_ERROR (0x1 << 5) > #define CLOSE_EXEC_QUEUES (0x1 << 2) > @@ -100,7 +101,7 @@ xe_legacy_test_mode(int fd, struct drm_xe_engine_class_instance *eci, > u64 exec_addr; > int e = i % n_exec_queues; > > - if (!i) { > + if (!i || flags & CANCEL) { > spin_opts.addr = base_addr + spin_offset; > xe_spin_init(&data[i].spin, &spin_opts); > exec_addr = spin_opts.addr; > @@ -155,7 +156,7 @@ xe_legacy_test_mode(int fd, struct drm_xe_engine_class_instance *eci, > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); > igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL)); > > - if (!use_capture_mode && !(flags & GT_RESET)) { > + if (!use_capture_mode && !(flags & (GT_RESET | CANCEL))) { > for (i = 1; i < n_execs; i++) > igt_assert_eq(data[i].data, 0xc0ffee); > } > diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c > index 72b85d3e7b..88e9df6fbb 100644 > --- a/tests/intel/xe_exec_reset.c > +++ b/tests/intel/xe_exec_reset.c > @@ -117,6 +117,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci, > #define PARALLEL (0x1 << 4) > #define CAT_ERROR (0x1 << 5) > #define PREEMPT (0x1 << 6) > +#define CANCEL (0x1 << 7) > > /** > * SUBTEST: %s-cat-error > @@ -302,6 +303,12 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, > * SUBTEST: cancel-preempt > * Description: Test job cancel with a preemptable job > * > + * SUBTEST: cancel-timeslice-preempt > + * Description: Test job cancel with 2 preemptable jobs > + * > + * SUBTEST: cancel-timeslice-many-preempt > + * Description: Test job cancel with many preemptable jobs > + * > * SUBTEST: gt-reset > * Description: Test GT reset > * > @@ -396,7 +403,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, > uint64_t exec_addr; > int e = i % n_exec_queues; > > - if (!i) { > + if (!i || flags & CANCEL) { > spin_opts.addr = base_addr + spin_offset; > xe_spin_init(&data[i].spin, &spin_opts); > exec_addr = spin_opts.addr; > @@ -451,7 +458,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, > xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); > xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, 3 * NSEC_PER_SEC); > > - if (!(flags & GT_RESET)) { > + if (!(flags & (GT_RESET | CANCEL))) { > for (i = 1; i < n_execs; i++) > igt_assert_eq(data[i].data, 0xc0ffee); > } > @@ -680,6 +687,20 @@ igt_main > break; > } > > + igt_subtest("cancel-timeslice-preempt") > + xe_for_each_engine(fd, hwe) { > + xe_legacy_test_mode(fd, hwe, 2, 2, CANCEL | PREEMPT, > + LEGACY_MODE_ADDR, false); > + break; > + } > + > + igt_subtest("cancel-timeslice-many-preempt") > + xe_for_each_engine(fd, hwe) { > + xe_legacy_test_mode(fd, hwe, 4, 4, CANCEL | PREEMPT, > + LEGACY_MODE_ADDR, false); > + break; > + } > + LGTM, Reviewed-by: Marcin Bernatowicz > igt_subtest("gt-reset") > xe_for_each_engine(fd, hwe) > xe_legacy_test_mode(fd, hwe, 2, 2, GT_RESET,