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Thu, 15 May 2025 15:49:58 +0000 (GMT) Message-ID: Date: Thu, 15 May 2025 10:49:58 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 46/50] ppc/xive2: Implement set_os_pending TIMA op To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?UTF-8?B?RnLDqWTDqXJpYyBCYXJyYXQ=?= , Glenn Miles , Caleb Schlossin References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-47-npiggin@gmail.com> Content-Language: en-US From: Mike Kowal In-Reply-To: <20250512031100.439842-47-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=etzfzppX c=1 sm=1 tr=0 ts=68260d2a cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=pGLkceISAAAA:8 a=jaoGCA84DIYCLCjvDVkA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE1NSBTYWx0ZWRfX+oZRioa5wpQ6 1VcpMRqQr3wGuNjzNHt87CzQSjmhrv783n81/e8RdmIVyfkJ0qrKI39bA6nQbIbNc9k88vFPD9z RzhXAinMHNeYzK4RS2XK68DJKayOZ2HEPF0xtwZ+l+posqY02+d1BAKbi1Daq8IM8kUi6sPYIxs jn2dWF6rnERKZvOUDFZTJQ285qWVECMLF2NeDjnf111O1QUzJrRdZL16JP0kVPvmQCOQ+nZ36d4 82QkpTuT45tiyNl/raweDE6o1mMEXCqPnpmwHjV/iIpjyCvt5erOnqK4HMqmk5BfnT1w+6B1wgl W1fUWMc4cP3DxWfC1XCvH5AXxvK/9dAAQWpeuej0H9bUFfBN15D5dcyVYkg1ZrUxsg5nlwN9hZ3 k+auur1p2Dh1QmSIwWPSfnLs83OT998w4aFP76x1VW78ereJTFaiMMswArffe4v91V8CpDh0 X-Proofpoint-ORIG-GUID: NCF4VzEltiSze7j56_K2LL1RGDwjME1L X-Proofpoint-GUID: Xp9RuHO0LazSfAd8QlT3BZn6d12_i8WS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_06,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 suspectscore=0 spamscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150155 Received-SPF: pass client-ip=148.163.156.1; envelope-from=kowal@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/11/2025 10:10 PM, Nicholas Piggin wrote: > xive2 must take into account redistribution of group interrupts if > the VP directed priority exceeds the group interrupt priority after > this operation. The xive1 code is not group aware so implement this > for xive2. Reviewed-by: Michael Kowal Thanks,  MAK > > Signed-off-by: Nicholas Piggin > --- > hw/intc/xive.c | 2 ++ > hw/intc/xive2.c | 28 ++++++++++++++++++++++++++++ > include/hw/ppc/xive2.h | 2 ++ > 3 files changed, 32 insertions(+) > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index 979031a587..dc64edf13d 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -747,6 +747,8 @@ static const XiveTmOp xive2_tm_operations[] = { > /* MMIOs above 2K : special operations with side effects */ > { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, true, false, > NULL, xive_tm_ack_os_reg }, > + { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, true, false, > + xive2_tm_set_os_pending, NULL }, > { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, true, false, > NULL, xive2_tm_pull_os_ctx }, > { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, true, false, > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index 392ac6077e..de1ccad685 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -1323,6 +1323,34 @@ void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, > xive2_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); > } > > +/* > + * Adjust the IPB to allow a CPU to process event queues of other > + * priorities during one physical interrupt cycle. > + */ > +void xive2_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, > + hwaddr offset, uint64_t value, unsigned size) > +{ > + Xive2Router *xrtr = XIVE2_ROUTER(xptr); > + uint8_t ring = TM_QW1_OS; > + uint8_t *regs = &tctx->regs[ring]; > + uint8_t priority = value & 0xff; > + > + /* > + * XXX: should this simply set a bit in IPB and wait for it to be picked > + * up next cycle, or is it supposed to present it now? We implement the > + * latter here. > + */ > + regs[TM_IPB] |= xive_priority_to_ipb(priority); > + if (xive_ipb_to_pipr(regs[TM_IPB]) >= regs[TM_PIPR]) { > + return; > + } > + if (xive_nsr_indicates_group_exception(ring, regs[TM_NSR])) { > + xive2_redistribute(xrtr, tctx, ring); > + } > + > + xive_tctx_pipr_present(tctx, ring, priority, 0); > +} > + > static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t target) > { > uint8_t *regs = &tctx->regs[ring]; > diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h > index c1ab06a55a..45266c2a8b 100644 > --- a/include/hw/ppc/xive2.h > +++ b/include/hw/ppc/xive2.h > @@ -130,6 +130,8 @@ void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, > hwaddr offset, uint64_t value, unsigned size); > void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, > hwaddr offset, uint64_t value, unsigned size); > +void xive2_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, > + hwaddr offset, uint64_t value, unsigned size); > void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, > uint64_t value, unsigned size); > uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,