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Message-ID: Date: Fri, 26 Sep 2025 14:34:08 +0300 User-Agent: Mozilla Thunderbird Subject: Re: [XEN][PATCH] x86/hvm: vlapic: fix RO bits emulation in LVTx regs To: Jan Beulich Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Alejandro Vallejo , Jason Andryuk , "xen-devel@lists.xenproject.org" References: <20250925195558.519568-1-grygorii_strashko@epam.com> <67dd3659-916b-4e64-afe2-e13fdc8d31f0@suse.com> Content-Language: en-US From: Grygorii Strashko In-Reply-To: <67dd3659-916b-4e64-afe2-e13fdc8d31f0@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: FR4P281CA0379.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:f7::11) To AS2PR03MB8907.eurprd03.prod.outlook.com (2603:10a6:20b:5e4::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS2PR03MB8907:EE_|DU0PR03MB9850:EE_ X-MS-Office365-Filtering-Correlation-Id: 13117261-a6e2-4269-e3e6-08ddfcf09c57 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; 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Usually RO/WI on most HW. >> For example, LAPIC MMIO "Write" will be ignored (WRMSR will trigger exception). Sorry, ignore ^ sentence. > > My remark was specifically about WRMSR, and what you say here contradicts ... > >>>> --- a/xen/arch/x86/hvm/vlapic.c >>>> +++ b/xen/arch/x86/hvm/vlapic.c >>>> @@ -880,6 +880,7 @@ void vlapic_reg_write(struct vcpu *v, unsigned int reg, uint32_t val) >>>> if ( vlapic_sw_disabled(vlapic) ) >>>> val |= APIC_LVT_MASKED; >>>> val &= array_access_nospec(vlapic_lvt_mask, (reg - APIC_LVTT) >> 4); >>>> + val &= ~(APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING); >>> >>> There shouldn't be a 2nd &= here; what needs adding should imo be added to >>> (really: removed from) vlapic_lvt_mask[]. >> >> I'll try it. >> >> (Orthogonal to this I wonder whether >>> guest_wrmsr_x2apic() wouldn't better use that array, too.) >> >> WRMSR checks for MBZ. RO bits are not MBZ, so masks are different. > > ... what you say here. Above reflects current code - guest_wrmsr_x2apic() allows valid RO bits, then vlapic_reg_write() ignores (W/I) them. That's why masks are different between guest_wrmsr_x2apic and vlapic_reg_write. > >>> While looking at this, don't we have an issue with CMCI as well? >> >> I see no APIC_CMCI write emulation. only read. > > guest_wrmsr_x2apic() has > > case APIC_CMCI: it will end up calling vlapic_reg_write() which doesn't have case statement for APIC_CMCI - write ignored. > >>> guest_{rd,wr}msr_x2apic() handle it, but vlapic_reg_write() doesn't. I.e. on >>> AMD we would fail to deliver #GP when the guest accesses it, while on Intel >>> we would lose the value written. And we also don't set its mask bit in >>> vlapic_do_init(). I guess I need to make a patch ... >> >> Is'n it depends on CMCI capability exposing to guest? > > Yes, that's part of what I was (effectively) saying. > >> (have no idea what's CMCI :) > > Corrected Machine Check Interrupt. Looking at: #define VLAPIC_VERSION 0x00050014 which means "Max LVT Entries" = 6 (5+1) Looking at linux kernel apic.c: #ifdef CONFIG_X86_MCE_INTEL if (maxlvt >= 6) { v = apic_read(APIC_LVTCMCI); if (!(v & APIC_LVT_MASKED)) apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); } #endif Which means Xen never really emulated APIC_CMCI, so wouldn't it be correct to just drop APIC_CMCI? Also, taking into account that it's Intel specific. -- Best regards, -grygorii