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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cee80eda4sm18108115e9.15.2026.09.02.14.30.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Sep 2026 14:30:09 -0700 (PDT) Message-ID: Date: Wed, 2 Sep 2026 23:30:07 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 03/11] hw/intc: clear pending bit on l2vic de-assertion Content-Language: en-US To: Brian Cain , qemu-devel@nongnu.org Cc: Pierrick Bouvier , Laurent Vivier , Helge Deller , Sid Manning References: <20260901173353.200474-1-brian.cain@oss.qualcomm.com> <20260901173353.200474-4-brian.cain@oss.qualcomm.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20260901173353.200474-4-brian.cain@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: wPSjAmfGGHbxHf5kyCDK_2do5y32Z86z X-Authority-Analysis: v=2.4 cv=L+wtheT8 c=1 sm=1 tr=0 ts=6a989565 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=CDaaqbpuOxbtrJYFCQUA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAyMDE5MCBTYWx0ZWRfX3UEDSh5mEKyp nvArbJfT3mFN9akyj+N2bNhcu7ePuIFBUjJ9Mf1Hgp5TFYaI5fu5zMVXJDm/gqTdDRzSYbn6nR1 8P8m2IpBuZDbfd9CLfZD//LPLOV7q3NeD8umwPfTM8V+6am2vix/Raegs1E2J1Aw+99qhBdgb/I A2HlHkYL0tBYiLLTtvoF/LYJxYoM0pNMOIhZdsfN5rinaLjxlHtl305exbF9eTqKUwP6/Hqm54Q ps+4bl8lOgWX6wnKroiJtUG1L5CoaPGRax9cSvzfn8u3StOn3yAQjrmM/M1EY4lQoj1OYaDbPzd oaRenQUjLEW+o6uyFf3mnZa7B+EiNOhWUQAHGNXEyqV4JwgDuEVYH4mxq8YotbLxH62+PNoM9Y2 lNGLDEX4m/IsbkHxOLm6rlczThfW8UnQg73Zmdc12lG5W77wqfD+sdrILyv2j554zE7QftX0d0E lhHuzexe9m6IvbeFXdQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAyMDE5MCBTYWx0ZWRfX9DYhIFYPo35i iXoGYq0pFRjVQwxNvVMJfgcVRo1C3pWzw4fK9lAhAH5vsE96RcOjXCRbydK2ROxjfIfHKvnVgyb b6bOapSq/uwr18AUiaqtln1+WHN7xWg= X-Proofpoint-ORIG-GUID: wPSjAmfGGHbxHf5kyCDK_2do5y32Z86z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-02_05,2026-09-02_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 impostorscore=0 phishscore=0 spamscore=0 suspectscore=0 adultscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609020190 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/9/26 19:33, Brian Cain wrote: > From: Sid Manning > > l2vic_set_irq() clears a level-triggered source's pending bit on > de-assertion, so a source that drops before it is latched into > int_status is not spuriously re-delivered on the next ciad. > Edge-triggered sources (int_type set) keep the pulse semantics they > already have via SOFT_INT/set_irq(level=1). > > Reviewed-by: Pierrick Bouvier > Signed-off-by: Brian Cain > --- > hw/intc/hex-l2vic.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/hw/intc/hex-l2vic.c b/hw/intc/hex-l2vic.c > index f07ec850d49..a986f0bdf35 100644 > --- a/hw/intc/hex-l2vic.c > +++ b/hw/intc/hex-l2vic.c > @@ -299,6 +299,8 @@ static void l2vic_set_irq(void *opaque, int irq, int level) > > if (level) { > set_bit32(irq, s->int_pending); > + } else if (!test_bit32(irq, s->int_type)) { > + clear_bit32(irq, s->int_pending); > } > l2vic_update(s, irq); I'm confused with l2vic_update() logic which seems to duplicate a bit. > } hw/intc/hex-l2vic.c-95- /* Edge or Level interrupt */ hw/intc/hex-l2vic.c:96: DECLARE_BITMAP32(int_type, L2VIC_INTERRUPT_MAX); Not obvious, so 0:edge and 1:level. Ah no... hw/intc/hex-l2vic.c-268- * Only auto-disable for edge-triggered interrupts (type=1). So 1:edge and 0:level? Tiny helpers can help to make the code more readable: static bool edge_triggered_irq(HexL2VICState *s, int irq) { return test_bit32(irq, s->int_type) == 1; }