From: Richard Henderson <richard.henderson@linaro.org>
To: matheus.ferst@eldorado.org.br, qemu-devel@nongnu.org,
qemu-ppc@nongnu.org
Cc: lucas.castro@eldorado.org.br, luis.pires@eldorado.org.br,
groug@kaod.org, david@gibson.dropbear.id.au
Subject: Re: [PATCH 19/33] target/ppc: Implement Vector Extract Double to VSR using GPR index insns
Date: Sat, 23 Oct 2021 13:01:35 -0700 [thread overview]
Message-ID: <c417d52e-6401-fa59-3dae-e51dfe523636@linaro.org> (raw)
In-Reply-To: <20211021194547.672988-20-matheus.ferst@eldorado.org.br>
On 10/21/21 12:45 PM, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> Implement the following PowerISA v3.1 instructions:
> vextdubvlx: Vector Extract Double Unsigned Byte to VSR using
> GPR-specified Left-Index
> vextduhvlx: Vector Extract Double Unsigned Halfword to VSR using
> GPR-specified Left-Index
> vextduwvlx: Vector Extract Double Unsigned Word to VSR using
> GPR-specified Left-Index
> vextddvlx: Vector Extract Double Unsigned Doubleword to VSR using
> GPR-specified Left-Index
> vextdubvrx: Vector Extract Double Unsigned Byte to VSR using
> GPR-specified Right-Index
> vextduhvrx: Vector Extract Double Unsigned Halfword to VSR using
> GPR-specified Right-Index
> vextduwvrx: Vector Extract Double Unsigned Word to VSR using
> GPR-specified Right-Index
> vextddvrx: Vector Extract Double Unsigned Doubleword to VSR using
> GPR-specified Right-Index
>
> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> ---
> target/ppc/helper.h | 4 +++
> target/ppc/insn32.decode | 12 +++++++++
> target/ppc/int_helper.c | 41 ++++++++++++++++++++++++++++-
> target/ppc/translate/vmx-impl.c.inc | 37 ++++++++++++++++++++++++++
> 4 files changed, 93 insertions(+), 1 deletion(-)
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 53c65ca1c7..ac8ab7e436 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -336,6 +336,10 @@ DEF_HELPER_2(vextuwlx, tl, tl, avr)
> DEF_HELPER_2(vextubrx, tl, tl, avr)
> DEF_HELPER_2(vextuhrx, tl, tl, avr)
> DEF_HELPER_2(vextuwrx, tl, tl, avr)
> +DEF_HELPER_5(VEXTDUBVLX, void, env, avr, avr, avr, tl)
> +DEF_HELPER_5(VEXTDUHVLX, void, env, avr, avr, avr, tl)
> +DEF_HELPER_5(VEXTDUWVLX, void, env, avr, avr, avr, tl)
> +DEF_HELPER_5(VEXTDDVLX, void, env, avr, avr, avr, tl)
>
> DEF_HELPER_2(vsbox, void, avr, avr)
> DEF_HELPER_3(vcipher, void, avr, avr, avr)
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 2eb7fb4e92..e438177b32 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -38,6 +38,9 @@
> %dx_d 6:s10 16:5 0:1
> @DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
>
> +&VA vrt vra vrb rc
> +@VA ...... vrt:5 vra:5 vrb:5 rc:5 ...... &VA
> +
> &VN vrt vra vrb sh
> @VN ...... vrt:5 vra:5 vrb:5 .. sh:3 ...... &VN
>
> @@ -347,6 +350,15 @@ VPEXTD 000100 ..... ..... ..... 10110001101 @VX
>
> ## Vector Permute and Formatting Instruction
>
> +VEXTDUBVLX 000100 ..... ..... ..... ..... 011000 @VA
> +VEXTDUBVRX 000100 ..... ..... ..... ..... 011001 @VA
> +VEXTDUHVLX 000100 ..... ..... ..... ..... 011010 @VA
> +VEXTDUHVRX 000100 ..... ..... ..... ..... 011011 @VA
> +VEXTDUWVLX 000100 ..... ..... ..... ..... 011100 @VA
> +VEXTDUWVRX 000100 ..... ..... ..... ..... 011101 @VA
> +VEXTDDVLX 000100 ..... ..... ..... ..... 011110 @VA
> +VEXTDDVRX 000100 ..... ..... ..... ..... 011111 @VA
> +
> VINSERTB 000100 ..... - .... ..... 01100001101 @VX_uim4
> VINSERTH 000100 ..... - .... ..... 01101001101 @VX_uim4
> VINSERTW 000100 ..... - .... ..... 01110001101 @VX_uim4
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index 5a925a564d..1577ea8788 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -1673,8 +1673,47 @@ VINSX(B, uint8_t)
> VINSX(H, uint16_t)
> VINSX(W, uint32_t)
> VINSX(D, uint64_t)
> -#undef ELEM_ADDR
> #undef VINSX
> +#define VEXTDVLX(NAME, TYPE) \
> +void glue(glue(helper_VEXTD, NAME), VLX)(CPUPPCState *env, ppc_avr_t *t, \
> + ppc_avr_t *a, ppc_avr_t *b, \
> + target_ulong index) \
> +{ \
> + const int array_size = ARRAY_SIZE(t->u8), elem_size = sizeof(TYPE); \
> + const target_long idx = index; \
> + \
> + if (idx < 0) { \
> + qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VEXTD" #NAME "VRX at"\
> + " 0x" TARGET_FMT_lx ", RC = " TARGET_FMT_ld " > %d\n", env->nip, \
> + 32 - elem_size - idx, 32 - elem_size); \
> + } else if (idx + elem_size <= array_size) { \
> + t->VsrD(0) = *(TYPE *)ELEM_ADDR(a, idx, elem_size); \
You need an unaligned load here.
> + t->VsrD(1) = 0; \
> + } else if (idx < array_size) { \
> + ppc_avr_t tmp = { .u64 = { 0, 0 } }; \
> + const int len_a = array_size - idx, len_b = elem_size - len_a; \
> + \
> + memmove(ELEM_ADDR(&tmp, array_size / 2 - elem_size, len_a), \
> + ELEM_ADDR(a, idx, len_a), len_a); \
> + memmove(ELEM_ADDR(&tmp, array_size / 2 - len_b, len_b), \
> + ELEM_ADDR(b, 0, len_b), len_b); \
You know tmp does not overlap the source; memcpy will do.
> + \
> + *t = tmp; \
> + } else if (idx + elem_size <= 2 * array_size) { \
> + t->VsrD(0) = *(TYPE *)ELEM_ADDR(b, idx - array_size, elem_size); \
Another unaligned load.
Or... we could set this up as
ppc_avr_t tmp[2] = { *a, *b };
memset(t, 0, sizeof(*t));
if (idx >= 0 && idx + elem_size <= sizeof(tmp)) {
memcpy(t + 8 - elem_size, (char *)&tmp + idx, elem_size);
}
... with some sort of host-endian adjustment which I'm too lazy to work out at the moment.
r~
next prev parent reply other threads:[~2021-10-23 20:03 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-21 19:45 [PATCH 00/33] PowerISA v3.1 instruction batch matheus.ferst
2021-10-21 19:45 ` [PATCH 01/33] target/ppc: introduce do_ea_calc matheus.ferst
2021-10-22 21:51 ` Richard Henderson
2021-10-22 21:57 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 02/33] target/ppc: move resolve_PLS_D to translate.c matheus.ferst
2021-10-22 22:01 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 03/33] target/ppc: Move load and store floating point instructions to decodetree matheus.ferst
2021-10-22 22:19 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 04/33] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions matheus.ferst
2021-10-22 22:24 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 05/33] target/ppc: Move LQ and STQ to decodetree matheus.ferst
2021-10-22 22:53 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 06/33] target/ppc: Implement PLQ and PSTQ matheus.ferst
2021-10-22 22:54 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 07/33] target/ppc: Implement cntlzdm matheus.ferst
2021-10-22 23:16 ` Richard Henderson
2021-10-26 14:33 ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 08/33] target/ppc: Implement cnttzdm matheus.ferst
2021-10-22 23:55 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 09/33] target/ppc: Implement pdepd instruction matheus.ferst
2021-10-23 0:04 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 10/33] target/ppc: Implement pextd instruction matheus.ferst
2021-10-23 0:26 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 11/33] target/ppc: Move vcfuged to vmx-impl.c.inc matheus.ferst
2021-10-23 0:31 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 12/33] target/ppc: Implement vclzdm/vctzdm instructions matheus.ferst
2021-10-23 0:34 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 13/33] target/ppc: Implement vpdepd/vpextd instruction matheus.ferst
2021-10-23 0:38 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 14/33] target/ppc: Implement vsldbi/vsrdbi instructions matheus.ferst
2021-10-23 4:07 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns matheus.ferst
2021-10-23 4:37 ` Richard Henderson
2021-10-23 4:40 ` Richard Henderson
2021-10-23 10:12 ` BALATON Zoltan
2021-10-23 18:36 ` Richard Henderson
2021-10-23 20:02 ` BALATON Zoltan
2021-10-23 20:09 ` Richard Henderson
2021-10-26 14:33 ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 16/33] target/ppc: Implement Vector Insert Word from GPR using Immediate insns matheus.ferst
2021-10-23 4:42 ` Richard Henderson
2021-10-26 14:33 ` Matheus K. Ferst
2021-10-26 16:58 ` Richard Henderson
2021-10-26 18:45 ` Paul A. Clarke
2021-10-27 11:49 ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 17/33] target/ppc: Implement Vector Insert from VSR using GPR index insns matheus.ferst
2021-10-23 4:48 ` Richard Henderson
2021-10-23 4:54 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 18/33] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree matheus.ferst
2021-10-23 4:53 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 19/33] target/ppc: Implement Vector Extract Double to VSR using GPR index insns matheus.ferst
2021-10-23 20:01 ` Richard Henderson [this message]
2021-10-21 19:45 ` [PATCH 20/33] target/ppc: Introduce REQUIRE_VSX macro matheus.ferst
2021-10-23 20:10 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree matheus.ferst
2021-10-23 20:34 ` Richard Henderson
2021-10-23 20:39 ` Richard Henderson
2021-10-23 20:46 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 22/33] target/ppc: moved stxvx and lxvx " matheus.ferst
2021-10-23 20:38 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 23/33] target/ppc: added the instructions LXVP and STXVP matheus.ferst
2021-10-23 20:48 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 24/33] target/ppc: added the instructions LXVPX and STXVPX matheus.ferst
2021-10-23 20:49 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 25/33] target/ppc: added the instructions PLXV and PSTXV matheus.ferst
2021-10-23 20:56 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 26/33] target/ppc: added the instructions PLXVP and PSTXVP matheus.ferst
2021-10-23 20:57 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 27/33] target/ppc: moved XXSPLTW to using decodetree matheus.ferst
2021-10-23 21:03 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 28/33] target/ppc: moved XXSPLTIB " matheus.ferst
2021-10-23 21:06 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 29/33] target/ppc: implemented XXSPLTI32DX matheus.ferst
2021-10-23 21:12 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 30/33] target/ppc: Implemented XXSPLTIW using decodetree matheus.ferst
2021-10-23 21:15 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 31/33] target/ppc: implemented XXSPLTIDP instruction matheus.ferst
2021-10-23 21:19 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 32/33] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions matheus.ferst
2021-10-23 21:24 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 33/33] target/ppc: Implement lxvkq instruction matheus.ferst
2021-10-23 21:29 ` Richard Henderson
2021-10-22 2:06 ` [PATCH 00/33] PowerISA v3.1 instruction batch Richard Henderson
2021-10-22 11:13 ` Matheus K. Ferst
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