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Wed, 11 Nov 2026 06:30:16 -0800 (PST) Message-ID: Date: Wed, 11 Nov 2026 15:30:15 +0100 X-Archived-By: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 24/30] x86emul: support APX+{LZ,POP}CNT insns From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Teddy Astie , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <17d56a5d-41f2-4691-aea7-d6dfdde5ad32@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <17d56a5d-41f2-4691-aea7-d6dfdde5ad32@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1794407417-1DA7E757-34D13772/10/78276251493 X-purgate-type: spam X-purgate-size: 6814 X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Besides adding table entries and case labels there's very little to do here; generic map 4 handling takes care of things. To aid making the connection between ABM and LZCNT (the sole insn the feature bit covers), amend the comment in cpufeatures.h at the same time. Signed-off-by: Jan Beulich --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -1154,6 +1154,16 @@ static const struct test bmi2[] = { INSN(shrx, f2, 0f38, f7, el, dq, no), }; +static const struct test lzcnt[] = { + INSN(lzcnt, , map4, f5, el, dq, no), + INSN(lzcntw, 66, map4, f5, el, w, no), +}; + +static const struct test popcnt[] = { + INSN(popcnt, , map4, 88, el, dq, no), + INSN(popcntw, 66, map4, 88, el, w, no), +}; + static const unsigned char vl_all[] = { VL_512, VL_128, VL_256 }; static const unsigned char vl_128[] = { VL_128 }; static const unsigned char vl_no128[] = { VL_512, VL_256 }; @@ -1745,6 +1755,8 @@ void evex_disp8_test(void *instr, struct RUN(bmi1); RUN(bmi2); RUN(cmpccxadd); + RUN(lzcnt); + RUN(popcnt); #undef RUN --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -2260,6 +2260,8 @@ static const struct evex { { { 0x84 }, 2, T, R, pfx_no, WIG, L0, SCC }, /* ctest */ { { 0x85 }, 2, T, R, pfx_no, Wn, L0, SCC }, /* ctest */ { { 0x85 }, 2, T, R, pfx_66, Wn, L0, SCC }, /* ctest */ + { { 0x88 }, 2, T, R, pfx_no, Wn, L0 }, /* popcnt */ + { { 0x88 }, 2, T, R, pfx_66, Wn, L0 }, /* popcnt */ { { 0x8f, 0xc0 }, 2, F, R, pfx_no, Wn, L0, ND }, /* pop2 */ { { 0xa5 }, 2, T, W, pfx_no, Wn, L0, ND }, /* shld */ { { 0xa5 }, 2, T, W, pfx_66, Wn, L0, ND }, /* shld */ @@ -2344,6 +2346,8 @@ static const struct evex { { { 0xf1 }, 2, T, R, pfx_66, Wn, L0 }, /* crc32 */ { { 0xf4 }, 2, T, R, pfx_no, Wn, L0 }, /* tzcnt */ { { 0xf4 }, 2, T, R, pfx_66, Wn, L0 }, /* tzcnt */ + { { 0xf5 }, 2, T, R, pfx_no, Wn, L0 }, /* lzcnt */ + { { 0xf5 }, 2, T, R, pfx_66, Wn, L0 }, /* lzcnt */ { { 0xf6, 0x00 }, 3, T, R, pfx_no, WIG, L0, SCC }, /* ctest */ { { 0xf6, 0x10 }, 2, T, W, pfx_no, WIG, L0, ND }, /* not */ { { 0xf6, 0x18 }, 2, T, W, pfx_no, WIG, L0, ND }, /* neg */ --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -2516,6 +2516,26 @@ int main(int argc, char **argv) (regs.eip != (unsigned long)&instr[5]) ) goto fail; printf("okay\n"); + + if ( true /* cpu_has_apx_nci_ndd_nf */ ) + { + cpu_policy.apx.apx_nci_ndd_nf = true; + + printf("%-40s", "Testing {nf}popcnt (%rdx),%rcx..."); + instr[0] = 0x62; instr[1] = 0xf4; instr[2] = 0xfc; instr[3] = 0x0c; + instr[4] = 0x88; instr[5] = 0x0a; + res[1] = 0x23456789; + regs.eflags = EFLAGS_MASK; + regs.rip = (unsigned long)&instr[0]; + rc = x86_emulate(&ctxt, &emulops); + if ( (rc != X86EMUL_OKAY) || regs.rcx != 34 || + (regs.eflags != EFLAGS_MASK) || + (regs.rip != (unsigned long)&instr[6]) ) + goto fail; + printf("okay\n"); + + cpu_policy.apx.apx_nci_ndd_nf = nci_ndd_nf; + } #endif } else --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -234,6 +234,7 @@ void wrpkru(unsigned int val); #define cpu_has_xgetbv1 (cpu_has_xsave && cpu_policy.xstate.xgetbv1) #define cpu_has_3dnow_ext cpu_policy.extd._3dnowext +#define cpu_has_lzcnt cpu_policy.extd.abm #define cpu_has_sse4a cpu_policy.extd.sse4a #define cpu_has_xop (cpu_policy.extd.xop && xcr0_mask(6)) #define cpu_has_fma4 (cpu_policy.extd.fma4 && xcr0_mask(6)) --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -730,6 +730,10 @@ static const struct map4_table { [vex_np] = { }, [vex_66] = { }, }, + [0x88] = { /* POPCNT ({,d,q}word) */ + [vex_np] = { .nf = true, .nci_ndd_nf = true }, + [vex_66] = { .nf = true, .nci_ndd_nf = true }, + }, [0x8f] = { /* Grp1a */ [vex_np] = { .nd = true }, }, @@ -792,6 +796,10 @@ static const struct map4_table { [vex_np] = { .nf = true, .nci_ndd_nf = true }, [vex_66] = { .nf = true, .nci_ndd_nf = true }, }, + [0xf5] = { /* LZCNT ({,d,q}word) */ + [vex_np] = { .nf = true, .nci_ndd_nf = true }, + [vex_66] = { .nf = true, .nci_ndd_nf = true }, + }, [0xf6] = { /* Grp3 (byte); most attributes depend on modrm_reg */ [vex_np] = { .byte = true, .nci_ndd_nf = true }, }, --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -5668,7 +5668,9 @@ x86_emulate( dst.val = (uint16_t)src.val; break; - case X86EMUL_OPC_F3(0x0f, 0xb8): /* popcnt r/m,r */ + case X86EMUL_OPC_F3 (0x0f, 0xb8): /* popcnt r/m,r */ + case X86EMUL_OPC_EVEX (4, 0x88): /* popcnt r/m,reg */ + case X86EMUL_OPC_EVEX_66(4, 0x88): /* popcnt r/m,r16 */ vcpu_must_have(popcnt); asm ( "popcnt %1,%0" : "=r" (dst.val) : "rm" (src.val) ); _regs.eflags &= ~EFLAGS_MASK; @@ -5709,8 +5711,12 @@ x86_emulate( } break; + case X86EMUL_OPC_EVEX (4, 0xf5): /* lzcnt r/m,reg */ + case X86EMUL_OPC_EVEX_66(4, 0xf5): /* lzcnt r/m,r16 */ + vcpu_must_have(lzcnt); + fallthrough; case X86EMUL_OPC(0x0f, 0xbd): /* bsr or lzcnt */ - if ( vex.pfx == vex_f3 ) + if ( vex.pfx == vex_f3 || state->promoted_evex ) emulate_2op_SrcV_srcmem("lzcnt", src, dst, _regs.eflags); else { --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -159,7 +159,7 @@ XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) / XEN_CPUFEATURE(SVM, 3*32+ 2) /*h Secure virtual machine */ XEN_CPUFEATURE(EXTAPIC, 3*32+ 3) /* Extended APIC space */ XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /*S CR8 in 32-bit mode */ -XEN_CPUFEATURE(ABM, 3*32+ 5) /*A Advanced bit manipulation */ +XEN_CPUFEATURE(ABM, 3*32+ 5) /*A LZCNT insn (Advanced Bit Manipulation) */ XEN_CPUFEATURE(SSE4A, 3*32+ 6) /*A SSE-4A */ XEN_CPUFEATURE(MISALIGNSSE, 3*32+ 7) /*A Misaligned SSE mode */ XEN_CPUFEATURE(3DNOWPREFETCH, 3*32+ 8) /*A 3DNow prefetch instructions */