From: Chris Wilson <chris@chris-wilson.co.uk>
To: Eric Anholt <eric@anholt.net>, Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.
Date: Wed, 25 Jan 2012 09:57:58 +0000 [thread overview]
Message-ID: <c55c5d$1p13hl@AZSMGA002.ch.intel.com> (raw)
In-Reply-To: <87vco0cwxy.fsf@eliezer.anholt.net>
On Tue, 24 Jan 2012 18:55:53 -0800, Eric Anholt <eric@anholt.net> wrote:
> On Sat, 21 Jan 2012 17:36:13 +0100, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Thu, Jan 19, 2012 at 10:50:06AM -0800, Eric Anholt wrote:
> > > Older specs claimed this was bit 11, but newer specs and the actual
> > > simulator code say it was bit 12. Regardless, we don't use MI_FLUSH,
> > > or try to enable it any more.
> > >
> > > Signed-off-by: Eric Anholt <eric@anholt.net>
> >
> > I'd like to amend this with the following (on this patch instead of the
> > other, so that ppl actually can find it with git blame):
> >
> > "Furthermore actually setting bit12 results in gpu hangs both on snb and
> > ivb. Ben Widawsky discovered a ppt that claims that both bit12 and bit11
> > must be set, but that doesn't help either. And last but not least,
> > MI_FLUSH seems to work regardless of the setting of these bits."
>
> I haven't seen bit12 hanging snb/ivb -- I only knew of it hanging ilk
> (since it doesn't exist there). On my snb, running xvideo so that
> MI_FLUSHes are generated by the userland (I think -- I haven't caught
> them in cat i915_batchbuffers | intel_dump_decode -), with
> intel_reg_read 0x209c saying 0x1240, things are going fine. Also with
> 0x209c saying 0x240 (the result of this patch).
The SNB Xv path, that is the code called by Gen6DisplayVideoTexture,
never used MI_FLUSH.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-01-25 9:58 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-01-19 18:50 [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting Eric Anholt
2012-01-19 18:50 ` [PATCH 2/2] drm/i915: Correct the bit number for the MI_FLUSH_ENABLE Eric Anholt
2012-01-21 16:36 ` Daniel Vetter
2012-01-25 2:55 ` Eric Anholt
2012-01-25 4:22 ` Ben Widawsky
2012-01-25 8:37 ` Daniel Vetter
2012-01-25 9:57 ` Chris Wilson [this message]
2012-01-25 10:41 ` Daniel Vetter
2012-01-25 18:31 ` Eric Anholt
2012-01-19 18:53 ` [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting Daniel Vetter
2012-01-19 18:54 ` Keith Packard
2012-01-19 18:59 ` Ben Widawsky
2012-01-19 19:36 ` Keith Packard
2012-01-20 19:16 ` Eric Anholt
2012-01-20 22:57 ` Ben Widawsky
2012-01-21 0:40 ` Eric Anholt
2012-01-21 4:47 ` Ben Widawsky
2012-01-21 10:57 ` Kenneth Graunke
2012-01-21 21:32 ` Ben Widawsky
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