From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 2/2] drm/i915: catch gtfifo errors on forcewake_put Date: Sat, 04 Feb 2012 10:59:52 +0000 Message-ID: References: <1328308301-28304-1-git-send-email-ben@bwidawsk.net> <1328308301-28304-2-git-send-email-ben@bwidawsk.net> <20120204021533.GA7186@snipes.kumite> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id A40F19E7CA for ; Sat, 4 Feb 2012 02:59:57 -0800 (PST) In-Reply-To: <20120204021533.GA7186@snipes.kumite> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, 3 Feb 2012 18:15:33 -0800, Ben Widawsky wrote: > On Fri, Feb 03, 2012 at 11:10:09PM +0000, Chris Wilson wrote: > > On Fri, 3 Feb 2012 14:31:41 -0800, Ben Widawsky wrote: > TBH, I don't really understand POSTING_READ that well. If it just > requires that any read request made it through to the MCH (or whatever), > then sure I can replace the POSTING_READ. Obviously though this is > reading GTFIFODBG, and not FORCEWAKE, so you tell me. The posting read is simply a PCI write/read ordering barrier. It can be a read of any mmio address and before it is performed all previous writes to mmio addresses must have been sent along the PCI and no subsequent write is allowed to emitted ahead of the read. Hmm, so since the writes are in fact weakly ordered (they are allowed to be emitted in any order so long as they not reordered past a read), we would strictly need a barrier in front of the write to disable forcewake if it were not for the buffering performed by the chip of mmio writes under rc6. -Chris -- Chris Wilson, Intel Open Source Technology Centre