From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF1CAC636CC for ; Thu, 16 Feb 2023 05:51:24 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8771E85AB3; Thu, 16 Feb 2023 06:51:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 56A1485AB2; Thu, 16 Feb 2023 06:51:19 +0100 (CET) Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by phobos.denx.de (Postfix) with ESMTP id 1091F85AB8 for ; Thu, 16 Feb 2023 06:51:04 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=yanhong.wang@starfivetech.com Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 6DEF324E1B5; Thu, 16 Feb 2023 13:50:59 +0800 (CST) Received: from EXMBX073.cuchost.com (172.16.6.83) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 16 Feb 2023 13:50:59 +0800 Received: from [192.168.120.49] (171.223.208.138) by EXMBX073.cuchost.com (172.16.6.83) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 16 Feb 2023 13:50:58 +0800 Message-ID: Date: Thu, 16 Feb 2023 13:50:57 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 14/17] riscv: dts: jh7110: Add initial StarFive JH7110 device tree Content-Language: en-US To: Conor Dooley , Sean Anderson CC: David Abdurachmanov , , Rick Chen , Leo , Lukasz Majewski , Lee Kuan Lim , Jianlong Huang , Emil Renner Berthing References: <20230118081132.31403-1-yanhong.wang@starfivetech.com> <20230118081132.31403-15-yanhong.wang@starfivetech.com> <022f9da1-75db-40e9-2823-dbbf1cb6f3f5@gmail.com> From: yanhong wang In-Reply-To: Content-Type: text/plain; charset="UTF-8" X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX073.cuchost.com (172.16.6.83) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On 2023/1/20 2:30, Conor Dooley wrote: > Hey Se=C3=A1n, David, >=20 > On Thu, Jan 19, 2023 at 01:26:52AM -0500, Sean Anderson wrote: >> On 1/19/23 01:18, David Abdurachmanov wrote: >> > On Wed, Jan 18, 2023 at 10:19 AM Yanhong Wang >> > wrote: >=20 >> > > + U74_4: cpu@4 { >> > > + compatible =3D "sifive,u74-mc", "riscv"; >> > > + reg =3D <4>; >> > > + d-cache-block-size =3D <64>; >> > > + d-cache-sets =3D <64>; >> > > + d-cache-size =3D <32768>; >> > > + d-tlb-sets =3D <1>; >> > > + d-tlb-size =3D <40>; >> > > + device_type =3D "cpu"; >> > > + i-cache-block-size =3D <64>; >> > > + i-cache-sets =3D <64>; >> > > + i-cache-size =3D <32768>; >> > > + i-tlb-sets =3D <1>; >> > > + i-tlb-size =3D <40>; >> > > + mmu-type =3D "riscv,sv39"; >> > > + next-level-cache =3D <&ccache>; >> > > + riscv,isa =3D "rv64imafdcbsu"; >> >=20 >> > Looking at SiFive U74 manuals, shouldn't this be RV64GC_Zba_Zbb_Ssco= fpmf? >> > U74 only supports Zba and Zbb bit manip extensions. >> > This is from the 21G3.02.00 release manual. >> >=20 >> > Looking more, S76 core is listed in the manual as supporting up to: >> > RV64IMAC_Zicsr_Zifencei_Zba_Zbb_Sscofpmf. >> >=20 >> > I almost forgot about _Zicsr_Zifencei (which are part of G). Shouldn= 't >> > those be listed too in riscv,isa? >=20 > AFAIU, Linux just assumes them since they weren't their own thing prior > to ISA spec 20191213. I think in- & ex- cluding them are both valid... > Yeah. >=20 >> AFAIK we don't support Z/X in U-Boot. >=20 > Does the U-Boot ISA string parsing not just ignore un-implemented > extensions? If it does ignore things you don't implement, then I think > including the Z extensions should be no harm. > IMO, it'd be nice to have this string match whatever the hardware can > support so that same Devicetree can be used for U-Boot & whatever OS it > is booting. >=20 > That said, I'm yet to be sure that this SoC supports Zba or Zbb. > I asked on the corresponding patchset for Linux and the answer I got, > not from the vendor, was that it did. > To what extent it might (or if it actually does) I have not yet > determined. It's not mentioned in any of the documentation that I have > got my hands on. > I have one of these boards, so am in the process of getting something > functional enough on it to actually test that. >=20 Refer to the corresponding manual,the ISA definition of S7 is: rv64imac_z= icsr_zba_zbb,=20 and the ISA definition of U7 is: rv64imafdc_zicsr_zba_zbb, which is consi= stent with linux. > Thanks! > Conor.