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Fri, 12 Aug 2022 14:39:32 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C01DE4C040; Fri, 12 Aug 2022 14:39:31 +0000 (GMT) Received: from [9.101.4.17] (unknown [9.101.4.17]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 12 Aug 2022 14:39:31 +0000 (GMT) Message-ID: Date: Fri, 12 Aug 2022 16:39:31 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH for-7.2 v4 01/11] ppc/pnv: add phb-id/chip-id PnvPHB3RootBus properties Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, clg@kaod.org References: <20220811163950.578927-1-danielhb413@gmail.com> <20220811163950.578927-2-danielhb413@gmail.com> From: Frederic Barrat In-Reply-To: <20220811163950.578927-2-danielhb413@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: YKb0WzPge7guuQZnu4vW6jfoz7_p9zZE X-Proofpoint-ORIG-GUID: 4MO-IT2QBwE7yJJ-OtRw4wYTRJjle1vy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-12_09,2022-08-11_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1015 spamscore=0 mlxscore=0 mlxlogscore=999 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208120040 Received-SPF: pass client-ip=148.163.158.5; envelope-from=fbarrat@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/08/2022 18:39, Daniel Henrique Barboza wrote: > We rely on the phb-id and chip-id, which are PHB properties, to assign > chassis and slot to the root port. For default devices this is no big > deal: the root port is being created under pnv_phb_realize() and the > values are being passed on via the 'index' and 'chip-id' of the > pnv_phb_attach_root_port() helper. > > If we want to implement user created root ports we have a problem. The > user created root port will not be aware of which PHB it belongs to, > unless we're willing to violate QOM best practices and access the PHB > via dev->parent_bus->parent. What we can do is to access the root bus > parent bus. > > Since we're already assigning the root port as QOM child of the bus, and > the bus is initiated using PHB properties, let's add phb-id and chip-id > as properties of the bus. This will allow us trivial access to them, for > both user-created and default root ports, without doing anything too > shady with QOM. > > Reviewed-by: Cédric Le Goater > Signed-off-by: Daniel Henrique Barboza > --- Reviewed-by: Frederic Barrat Fred > hw/pci-host/pnv_phb3.c | 50 ++++++++++++++++++++++++++++++++++ > include/hw/pci-host/pnv_phb3.h | 9 +++++- > 2 files changed, 58 insertions(+), 1 deletion(-) > > diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c > index d4c04a281a..af8575c007 100644 > --- a/hw/pci-host/pnv_phb3.c > +++ b/hw/pci-host/pnv_phb3.c > @@ -1006,6 +1006,11 @@ void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb) > &phb->pci_mmio, &phb->pci_io, > 0, 4, TYPE_PNV_PHB3_ROOT_BUS); > > + object_property_set_int(OBJECT(pci->bus), "phb-id", phb->phb_id, > + &error_abort); > + object_property_set_int(OBJECT(pci->bus), "chip-id", phb->chip_id, > + &error_abort); > + > pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb); > } > > @@ -1105,10 +1110,55 @@ static const TypeInfo pnv_phb3_type_info = { > .instance_init = pnv_phb3_instance_init, > }; > > +static void pnv_phb3_root_bus_get_prop(Object *obj, Visitor *v, > + const char *name, > + void *opaque, Error **errp) > +{ > + PnvPHB3RootBus *bus = PNV_PHB3_ROOT_BUS(obj); > + uint64_t value = 0; > + > + if (strcmp(name, "phb-id") == 0) { > + value = bus->phb_id; > + } else { > + value = bus->chip_id; > + } > + > + visit_type_size(v, name, &value, errp); > +} > + > +static void pnv_phb3_root_bus_set_prop(Object *obj, Visitor *v, > + const char *name, > + void *opaque, Error **errp) > + > +{ > + PnvPHB3RootBus *bus = PNV_PHB3_ROOT_BUS(obj); > + uint64_t value; > + > + if (!visit_type_size(v, name, &value, errp)) { > + return; > + } > + > + if (strcmp(name, "phb-id") == 0) { > + bus->phb_id = value; > + } else { > + bus->chip_id = value; > + } > +} > + > static void pnv_phb3_root_bus_class_init(ObjectClass *klass, void *data) > { > BusClass *k = BUS_CLASS(klass); > > + object_class_property_add(klass, "phb-id", "int", > + pnv_phb3_root_bus_get_prop, > + pnv_phb3_root_bus_set_prop, > + NULL, NULL); > + > + object_class_property_add(klass, "chip-id", "int", > + pnv_phb3_root_bus_get_prop, > + pnv_phb3_root_bus_set_prop, > + NULL, NULL); > + > /* > * PHB3 has only a single root complex. Enforce the limit on the > * parent bus > diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h > index bff69201d9..4854f6d2f6 100644 > --- a/include/hw/pci-host/pnv_phb3.h > +++ b/include/hw/pci-host/pnv_phb3.h > @@ -104,9 +104,16 @@ struct PnvPBCQState { > }; > > /* > - * PHB3 PCIe Root port > + * PHB3 PCIe Root Bus > */ > #define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root" > +struct PnvPHB3RootBus { > + PCIBus parent; > + > + uint32_t chip_id; > + uint32_t phb_id; > +}; > +OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3RootBus, PNV_PHB3_ROOT_BUS) > > /* > * PHB3 PCIe Host Bridge for PowerNV machines (POWER8)